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Old 05-19-2009, 11:00 PM
FPGA Journal Update
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Default FPGA Journal Update Vol XXIII no. 07

FPGA Journal Update




a techfocus media publication :: May 19, 2009 :: volume XXIII, no. 07











FROM THE EDITOR



This week, we're un-bleeping the pseudo-expletive of one of the largest EDA vendors. Cadence has released a product specifically for FPGA design. After we picked our jaws up off the ground, we discovered that we were pleasantly surprised. Combining the company's popular PCB tools with Taray's 7Circuits product, the company has just launched "FPGA System Planner". Our latest feature has the details.

Thanks for reading! If there's anything we can do to make our publications more useful to you, please let us know at:comments (AT) fpgajournal (DOT) com. If you'd rather sound off in public, please post your comments or questions in our Journal Forums.



Kevin Morris – Editor in Chief
Techfocus Media, Inc.











EVENTS & ANNOUNCEMENTS











STAND OUT: MOVE TO ALTIUM'S NEXT GENERATION ELECTRONICS DESIGN SOLUTION. Altium Designer for US$195 per month with continuous updates. FPGA implementation, schematic capture and PCB layout in a single application, out of the box!

Find out about other license options and download a 30-day trial here





















Take our BRAND NEW
SUPER QUICK, JUST A COUPLE OF QUESTIONS,
WON'T TAKE MUCH TIME AT ALL (WE PROMISE)
2009 Journal Reader Survey.

WEIGH IN NOW!!

















LATEST NEWS



May 19, 2009



National Instruments LabVIEW Provides Off-the-Shelf EPICS Integration for Particle Accelerator and Tokamak Control



Mixel Celebrates 10 Years of Mixed-Signal Excellence



Tokyo Electron Device Announces ASIC/LSI Prototyping Board Released Featuring DDR3 SDRAM and LV-DDR2 SDRAM



May 18, 2009



Real Intent Announces New Releases of Ascent and Meridian



Atmel Rhino+ USB Demonstration/Evaluation Kit for SHA-256 Cryptographic Authentication Chip



Altera Ships Arria II GX FPGAs: High-Performance, Low-Cost Transceiver FPGAs for 3-Gbps Applications



May 14, 2009



Texas Instruments introduces first SuperSpeed USB-compliant transceiver test chip



Synopsys PrimeTime PX Power Analysis Solution Achieves Broad Market Adoption










CURRENT FEATURE ARTICLES



Cadence Uses the F Word
FPGA PCB Co-design Debuts
(Kevin Morris)
Fusion Finds its Groove
Actel Sees Applications for FPGA/Analog Hybrid
(Kevin Morris)
Need to Cut Cost, Risk, Time?
Choose the Right FPGA Design Solution
by Daniel Platzker, Mentor Graphics Corporation
The Presence of Giants
2009 Inventors Hall of Fame Induction Tells a Story
(Kevin Morris)
Chef's Menu
Xilinx 11.1 Offers the Tools You Actually Need
(Kevin Morris)
Altium Goes for the Masses
Breaking the EDA Mold... Again
(Kevin Morris)



JOURNAL WEBCASTS



NEW! CHALK TALK FPGA - PCB Co-Design Done The Right Way. Join Amelia Dalton as she talks with Hemant Shah of Cadence Design Systems about new ways to manage the complex issues that arise when trying to optimize pin assignments for both FPGAs and PCBs. (Cadence)

FPGAs Verifying FPGAs. Advanced FPGAs now require a more rigorous verification approach or designers risk spending months in the lab trying to debug their designs in-system. Learn how Device Native® verification integrates seamlessly with your existing FPGA design tools and delivers significant productivity improvements for verification and debug. (GateRocket)

CHALK TALK Confirma™: The Next Era Of Prototyping. Struggling with FPGA prototyping boards? Join Amelia Dalton as she talks with Juergen Jaeger of Synopsys about the Next Era of Rapid Prototyping. (Synopsys)

CHALK TALK From Desktop to Target: What You Need From A Development Suite. Is embedded software development and debug a challenge for your team? Join Amelia Dalton as she chats with Jit Sivalogan of Mentor Graphics about setting up a productive environment for embedded development. (Mentor Graphics)

CHALK TALK Simplified Verification of DSP Algorithms in Hardware. Moving algorithms from MATLAB to FPGAs? Join Amelia Dalton as she explores options for verifying DSP designs implemented in FPGAs with Tim Vanevenhoven from Xilinx. (Xilinx)



[click here for more webcasts]












Cadence Uses the F Word
FPGA PCB Co-design Debuts
(Kevin Morris)

Mentor brought us Leonardo, Precision, ModelSim, and Catapult.  Synopsys sells Synplify and HAPS.  Magma brought us Palace and Blast FPGA.  Big EDA companies have had anything from a toenail to a whole leg dangling in the FPGA pool for years now... except Cadence.  

Like a politician skillfully skirting a controversial issue, Cadence deftly danced around the FPGA domain without touching - one big boot in the IC/ASIC design world, and another firmly planted at the board/system level - with the word "FPGA" never crossing their lips.  When you were designing a board with your Cadence tools, you could put all sorts of parts down - ASICs, standard parts, ASSPs, analog... you know - anything, really.  

Now, all that seems to be changing.  This week, Cadence announced a new addition to both their OrCad and Allegro PCB design suites - "FPGA System Planner."  There!  They said it!  And, it's even the first word in the title. [more]






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