FPGA Central

FPGA Journal Update




a techfocus media publication :: May 12, 2009 :: volume XXIII, no. 06











FROM THE EDITOR



This week, we take a look at Actel's Fusion mixed-signal FPGAs. When Fusion was first introduced, we figured it was a particularly potent platform for engineers to show their creative side. Our latest feature explains.

Also new this week, Daniel Platzker of Mentor Graphics talks about the choice between FPGA vendor-supplied tools and third-party EDA tools for FPGA design. The tool decision is a critical one for many design teams, and it pays to evaluate all the options.

Thanks for reading! If there's anything we can do to make our publications more useful to you, please let us know at:comments (AT) fpgajournal (DOT) com. If you'd rather sound off in public, please post your comments or questions in our Journal Forums.



Kevin Morris – Editor in Chief
Techfocus Media, Inc.











EVENTS & ANNOUNCEMENTS











STAND OUT: MOVE TO ALTIUM'S NEXT GENERATION ELECTRONICS DESIGN SOLUTION. Altium Designer for US$195 per month with continuous updates. FPGA implementation, schematic capture and PCB layout in a single application, out of the box!

Find out about other license options and download a 30-day trial here





















Take our BRAND NEW
SUPER QUICK, JUST A COUPLE OF QUESTIONS,
WON'T TAKE MUCH TIME AT ALL (WE PROMISE)
2009 Journal Reader Survey.

WEIGH IN NOW!!

















LATEST NEWS



May 12, 2009



Impulse CoValidator™ Automatically Generates ModelSim® FPGA Test Benches from C



FPGAs and Embedded Processors Technical Course



Tundra Semiconductor Announces RapidIO System Modeling Tool



GE Fanuc Intelligent Platforms Secures Order From Aselsan For Rugged Signal Processor Subsystem



Agilent Technologies Introduces Education Kits for Analog, Digital and RF Engineering Curriculum



Percello has Successfully Completed PRC6000 Verification



May 11, 2009



Curtiss-Wright Controls Announces 3U VPX Xilinx® FPGA Processor Board and Single Board Computer Solution



S2C Releases TAI Player Pro Software Version 3.1 with Multi-FPGA Internal Logic Analyzer



New Xilinx Virtex-5Q FPGA Family Delivers Higher Performance and Advanced Security Technologies for Defense Systems



Pigeon Point Systems Announces MicroTCA Carrier Management Controller BMR Starter Kit using Fusion Mixed-Signal FPGA



Synopsys IC Validator Adopted by NVIDIA for Sign-off Physical Verification



Pigeon Point Systems Announces Module Management Controller BMR Starter Kit Using Renesas H8S/2472



Synopsys Launches IC Validator, Offers Significant Reduction in Physical Verification Turnaround Time for Advanced Designs



SiliconBlue iCE65™ mobileFPGA™ Family Strengthens Consumer Handheld Leadership with World’s First Wafer Level Chip Scale Package SRAM FPGAs



May 7, 2009



Ericsson Power Block provides flexible, highly efficient power solution for processors



May 6, 2009



Achronix Taps Signali for 10/40/100Gbps Encryption IP in World’s Fastest FPGAS



Curtiss-Wright Controls Debuts New High Resolution Dual-Channel ADC FMC Card for Rugged DSP Applications



eASIC Accelerates DSP Market Momentum with New IP cores



AdvancedIO® Systems Announces expressXG™ Framework for Rapid High-Bandwidth Application Development



Pigeon Point Systems at the MicroTCA Summit 2009










CURRENT FEATURE ARTICLES



Fusion Finds its Groove
Actel Sees Applications for FPGA/Analog Hybrid
(Kevin Morris)
Need to Cut Cost, Risk, Time?
Choose the Right FPGA Design Solution
by Daniel Platzker, Mentor Graphics Corporation
The Presence of Giants
2009 Inventors Hall of Fame Induction Tells a Story
(Kevin Morris)
Chef's Menu
Xilinx 11.1 Offers the Tools You Actually Need
(Kevin Morris)
Altium Goes for the Masses
Breaking the EDA Mold... Again
(Kevin Morris)
Preaching to the Choir
Proselytizing Programmable Logic
(Kevin Morris)




JOURNAL WEBCASTS

FPGAs Verifying FPGAs. Advanced FPGAs now require a more rigorous verification approach or designers risk spending months in the lab trying to debug their designs in-system. Learn how Device Native® verification integrates seamlessly with your existing FPGA design tools and delivers significant productivity improvements for verification and debug. (GateRocket)

CHALK TALK Confirma™: The Next Era Of Prototyping. Struggling with FPGA prototyping boards? Join Amelia Dalton as she talks with Juergen Jaeger of Synopsys about the Next Era of Rapid Prototyping. (Synopsys)

CHALK TALK From Desktop to Target: What You Need From A Development Suite. Is embedded software development and debug a challenge for your team? Join Amelia Dalton as she chats with Jit Sivalogan of Mentor Graphics about setting up a productive environment for embedded development. (Mentor Graphics)

CHALK TALK Simplified Verification of DSP Algorithms in Hardware. Moving algorithms from MATLAB to FPGAs? Join Amelia Dalton as she explores options for verifying DSP designs implemented in FPGAs with Tim Vanevenhoven from Xilinx. (Xilinx)

CHALK TALK Using Embedded Hypervisors in Mobile Devices. Join Amelia Dalton as she explores the use of embedded hypervisors to create safe and secure software for mobile devices with Rob McCammon of Open Kernel Labs. (Open Kernel Labs)

[click here for more webcasts]












Fusion Finds its Groove
Actel Sees Applications for FPGA/Analog Hybrid (Kevin Morris)

Many times, we create a new technology with the knowledge that it has tremendous potentia but without a clear idea of how it will ultimately be used.  Or, we create a solution to one problem only to find later that our invention was even more useful in some completely different area.  We throw our new creation out to the public and are amazed when someone comes up with a far more clever way to use it than we had ever envisioned.

This may be the case with Actel's "Fusion" family of analog-capable FPGAs.  Sure, the company had a pretty good idea that engineers would find the combination of programmable digital fabric and real analog I/O useful, but we always suspected that the "killer apps" for Fusion would be discovered by the engineers that started using the devices, not by the factory. [more]








Need to Cut Cost, Risk, Time?
Choose the Right FPGA Design Solution
(Daniel Platzker, Mentor Graphics Corporation)

Many project teams move from ASICs to FPGAs to avoid high NRE costs, and to reduce the risk of re-spin and shorten time-to-market. But while FPGA technology offers these advantages, the development process itself requires equal attention. In fact, some ASIC/ASSP proponents argue that a large part of the design cost is incurred during the development phases including architectural exploration, design, and verification, thereby reducing the cost savings and time-to-market benefits of switching from ASICs to FPGAs.

For this reason, executives and project managers need to carefully consider their concept-to-PCB development approach. Is the process predictable, well integrated, and consistent from project to project? Does it allow for flexibility to move from one FPGA vendor to another as project requirements change? These are methodology and tool flow questions, and they impact the bottom line. In a down economy such as today’s, design teams are expected to cut costs yet still release innovative (i.e., “increasingly complex&rdquo products and to finish their projects on time. If system houses want to truly leverage the benefits of FPGAs, they have to think about how their tools and methodologies help them minimize cost, mitigate risk, and shorten time-to-market. [more]






You're receiving this newsletter because you subscribed at our web site www.fpgajournal.com.
If someone forwarded this newsletter to you and you'd like to receive your own free subscription, go to: www.fpgajournal.com/update.
If at any time, you would like to unsubscribe, click here. (But we hope you don't.)
If you have any questions or comments, send them to comments (AT) fpgajournal (DOT) com.



All material copyright © 2003-2009 techfocus media, inc. All rights reserved.
Privacy Statement