FPGA Central

FPGA Journal Update




a techfocus media publication :: April 7, 2009 :: volume XXIII, no. 01











FROM THE EDITOR



FPGAs continue to strip market share and design starts from ASIC. With current estimates putting FPGA design starts as much as 50X those of their "larger" competitors, why don't FPGA companies just declare victory and move on? Of course, it's not as simple as that. Our latest feature looks at the issues.

Also new this week is a contributed article from Suhel Dhanani and Girish Malipeddi of Altera who tell us about using FPGAs to design image format converters for broadcast systems. Because of the many variables and subtle differences between systems, the flexibility of FPGAs comes in very handy.

Thanks for reading! If there's anything we can do to make our publications more useful to you, please let us know at:comments (AT) fpgajournal (DOT) com. If you'd rather sound off in public, please post your comments or questions in our Journal Forums.



Kevin Morris – Editor in Chief
Techfocus Media, Inc.











EVENTS & ANNOUNCEMENTS











No Assembly Required. The use of FPGAs for ASIC or SoC design verification is no longer the “ad-hoc / assembly required” methodology it once was; It has evolved into a truly productive and high-performance ASIC verification solution. Learn more about Synopsys’ Confirma platform – the only complete ASIC prototyping solution.
More info





















Synplify Premier for Single-FPGA ASIC Prototyping
-Accepts RTL & SDC constraint input compatible with DC -Integrated RTL debug for in-system logic verification -Seamless integration with HAPS prototyping hardware -Includes DesignWare support & gated clock conversion
Click here to learn more.





















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LATEST NEWS



April 7, 2009



IZT Introduces Location Finding Software for Its IZT R3000 Receiver Series



Real Intent, Verific Celebrate Eight-Year Collaborative Partnership



Olympus Selects Synfora Algorithmic Synthesis Design Tools for Advanced Image Processing IC Development



April 6, 2009



Altera and The MathWorks Showcase Their End-to-End Military DSP Development Capabilities



Mentor Graphics Unveils Advanced Low Power Features in its Olympus-SoC Place-and-Route Platform



Blue Pearl Software Launches JumpStart Program for Startups



Pentek Announces a Multifrequency Clock Synthesizer Built for Signal Quality



April 2, 2009



Xilinx Starts Shipments of Virtex-6 FPGAs



April 1, 2009



Altera's 40-nm Stratix IV GX FPGAs Achieve PCI-SIG Compliance for the PCI Express 2.0 Architecture



Actel Now Shipping the IGLOO PLUS Starter Kit









CURRENT FEATURE ARTICLES



Kicking a Dead Horse
FPGAs Going the Distance Against ASIC
(Kevin Morris)
Building ‘Image Format Conversion’ Designs for Broadcast Systems
by Suhel Dhanani & Girish Malipeddi, Altera Corporation
Retro Revolution
The New Vintage FPGAs
(Kevin Morris)
Superlative Soup
The Three Biggest Baddest FPGAs
(Kevin Morris)
GateRocket Blasts Off
FPGAs Verifying FPGAs (Kevin Morris)
How Physical Synthesis Enables FPGA Design Productivity
by Ajay Jagtiani, Altera Corporation
FPGAs and the IC Bubble
The Techonomics of Programmability (Kevin Morris)



JOURNAL WEBCASTS



CHALK TALK Confirma™: The Next Era Of Prototyping. Struggling with FPGA prototyping boards? Join Amelia Dalton as she talks with Juergen Jaeger of Synopsys about the Next Era of Rapid Prototyping. (Synopsys)

CHALK TALK From Desktop to Target: What You Need From A Development Suite. Is embedded software development and debug a challenge for your team? Join Amelia Dalton as she chats with Jit Sivalogan of Mentor Graphics about setting up a productive environment for embedded development. (Mentor Graphics)

CHALK TALK Simplified Verification of DSP Algorithms in Hardware. Moving algorithms from MATLAB to FPGAs? Join Amelia Dalton as she explores options for verifying DSP designs implemented in FPGAs with Tim Vanevenhoven from Xilinx. (Xilinx)

CHALK TALK Using Embedded Hypervisors in Mobile Devices. Join Amelia Dalton as she explores the use of embedded hypervisors to create safe and secure software for mobile devices with Rob McCammon of Open Kernel Labs. (Open Kernel Labs)



[click here for more webcasts]












Kicking a Dead Horse
FPGAs Going the Distance Against ASIC
(Kevin Morris)

Imagine seeing the following copy in a modern ad:  "The new BMW 5-series sedan outperforms the horse and buggy in every important way.  Your family will travel farther in a day and arrive less fatigued thanks to our superior cruising speed, climate-controlled cabin, and luxurious upholstery.  It's so much easier to use as well - no more hitching up the team before you start, and no more watering, feeding, and grooming at the end of the day.  You just turn the key and drive away.  Simple as that. So, before you snap up that new stallion you've been eyeing - consider a car instead."

You'd probably feel like our Bavarian auto-marketers were out of touch with the times.  Certainly, there was a time when the main mission of the auto industry was replacement of horse-drawn conveyances, but there came a time when the automobile won, and marketers shifted their sights to more serious competition. [more]







Building ‘Image Format Conversion’ Designs for Broadcast Systems
by Suhel Dhanani & Girish Malipeddi, Altera Corporation



Image format conversion is commonly implemented within various broadcast infrastructure systems such as servers, switchers, head-end encoders, and specialty studio displays.

At the basic level, the need for image format conversion is driven by the multitude of input image formats that must be converted to high definition (HD) or a different resolution before being stored, encoded, or displayed.

The broadcast infrastructure is a fragmented market with every vendor having slightly different ‘image format conversion’ requirements – be it the number of channels, the output resolution, progressive vs. interlaced image processing, etc. Also different characteristics are important within different sub-segments. [more]






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