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Old 03-25-2009, 08:10 AM
FPGA Journal Update
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Default FPGA Journal Update Vol XXII no. 12

FPGA Journal Update




a techfocus media publication :: March 24, 2009 :: volume XXII, no. 12











FROM THE EDITOR



This week, we pull out the FPGA Journal centerfolds - the highest-end chips that we all dream about designing with someday, while we calmly place orders for the more "normal" devices that actually fit our designs. In the past year, three companies have introduced FPGAs that set new standards in size, performance, bandwidth, and DSP power. Our latest feature takes a look.

Thanks for reading! If there's anything we can do to make our publications more useful to you, please let us know at:comments (AT) fpgajournal (DOT) com. If you'd rather sound off in public, please post your comments or questions in our Journal Forums.



Kevin Morris – Editor in Chief
Techfocus Media, Inc.











EVENTS & ANNOUNCEMENTS











Introducing Xilinx® Virtex®-6 and Spartan®-6 FPGA Families. The Programmable Foundation for Targeted Design Platforms Reduce system cost by up to 50% - Lower power consumption by 65% Shrink development time by 50%.
Attend webcast and download documentation now





















Take our BRAND NEW
SUPER QUICK, JUST A COUPLE OF QUESTIONS,
WON'T TAKE MUCH TIME AT ALL (WE PROMISE)
2009 Journal Reader Survey.

WEIGH IN NOW!!

















LATEST NEWS



March 24, 2009



Micram Announces Broad Range of Silicon for 100G Development



Xilinx Demonstrates Next-Generation 100GE Interface with Best-in-Class Ecosystem Support at OFC/NFOEC Convention



QuickLogic to Introduce New CSSP Solutions at Globalpress Electronics Summit



Altera Showcases Its Embedded Portfolio at ESC 2009--Visit Altera in Booth 1044



March 23, 2009



Xilinx at ESC Silicon Valley 2009



Sarnoff Europe Announces Silicon Proven ESD Cells for UMC 65nm, 0.13um CMOS and 0.18um HV CMOS Under New Low-cost Business Model



K-micro Introduces Second Generation Burst Mode CDR SerDes for GPON OLTs



March 20, 2009



Design Analysis Ericsson GSM900MHz dTRU Radio Transceiver Features Component and Semiconductor Suppliers



Robotics Trends Announces Stimulus Pricing For Robobusiness Conference & Exposition 2009



Addition of 10A and 16A SIP models extends choice of OKAMI™ DOSA-compliant Point-of-Load DC/DC Converters



March 19, 2009



NetLogic Microsystems Demonstrates the Industry’s First 100GE PHY Solution Supported by a Broad 100GE Eco-System at OFC/NFOEC 2009



Sarance Technologies Releases 40GE and 100GE IP for General Availability



XJTAG Unveils XJFlash to Speed Boundary Scan Flash Memory Programming



March 18, 2009



Tokyo Electron Device Announces Quad Virtex-5 FPGA Platform for High-Speed Computing





CURRENT FEATURE ARTICLES



Superlative Soup
The Three Biggest Baddest FPGAs
(Kevin Morris)
GateRocket Blasts Off
FPGAs Verifying FPGAs (Kevin Morris)
How Physical Synthesis Enables FPGA Design Productivity
by Ajay Jagtiani, Altera Corporation
FPGAs and the IC Bubble
The Techonomics of Programmability (Kevin Morris)
A Synthesis & Partitioning Strategy for Effective Multi-FPGA Prototyping
by Nang-Ping Chen, Auspy, Inc. and Ehab Mohsen, Mentor Graphics
Simplifying DDR
Mentor’s New DDR Wizard (Bryon Moyer)
Free Linux Microprocessor*
(Some Restrictions Apply)
(Jim Turley)




JOURNAL WEBCASTS



CHALK TALK Confirma™: The Next Era Of Prototyping. Struggling with FPGA prototyping boards? Join Amelia Dalton as she talks with Juergen Jaeger of Synopsys about the Next Era of Rapid Prototyping. (Synopsys)

CHALK TALK From Desktop to Target: What You Need From A Development Suite. Is embedded software development and debug a challenge for your team? Join Amelia Dalton as she chats with Jit Sivalogan of Mentor Graphics about setting up a productive environment for embedded development. (Mentor Graphics)

CHALK TALK Simplified Verification of DSP Algorithms in Hardware. Moving algorithms from MATLAB to FPGAs? Join Amelia Dalton as she explores options for verifying DSP designs implemented in FPGAs with Tim Vanevenhoven from Xilinx. (Xilinx)

CHALK TALK Using Embedded Hypervisors in Mobile Devices. Join Amelia Dalton as she explores the use of embedded hypervisors to create safe and secure software for mobile devices with Rob McCammon of Open Kernel Labs. (Open Kernel Labs)



[click here for more webcasts]












Superlative Soup
The Three Biggest Baddest FPGAs

Many of us who wound up in engineering-related careers were fascinated with technology as kids.  Whether we were reading about cars, airplanes, computers, or hi-fi gear, we were intrigued by the latest and greatest of whatever genre we were investigating.  What was the fastest car - the biggest airplane - the most powerful sound system?  The exotic and superlative held a special fascination, often manifest as posters hanging on our walls or as the topic of playground discussion.  “Nuh-uh, the Lambo has a top speed of almost 200MPH – way faster than that lame-o Ferrari on your poster!”  It’s a funny thing to hear coming from a person who is about to jump on a five speed bike with a banana seat and squeak his way down the sidewalk at 8MPH. 

Today, we’re older, wiser, and more sophisticated.  We don’t just read about cool technology, we create it – for a living.  The allure of the superlative is still there, however, catching our eye from the corners.  Marketing people know this.  That’s why press releases often contain words like “world’s largest” or “industry’s fastest.” 

Over the past year in the FPGA world, we’ve had to tear down our posters and replace them with new ones.  The biggest, fastest, highest-bandwidth FPGAs are all new – and last year’s superstars have faded into relative obscurity.  How big, fast, and bandwidth-laden are the new champions?  How about a new Xilinx FPGA equal to about four of the largest Virtex-4 parts from a couple years back?  Or check out the Altera device with a total of 48 multi-gigabit transceivers – half of them capable of operating at speeds up to 11.3 Gbps? And, let’s also take a look at the Achronix Speedster – with internal speeds up to a blazing 1.5 GHz.  If FPGA designers still hung posters on their walls, chances are that one of these three bad boys would be up there - looking kinda boring by poster standards, actually, but nonetheless proud of their technological achievements. [more]











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