FPGA Central

FPGA Journal Update




a techfocus media publication :: March 10, 2009 :: volume XXII, no. 10











FROM THE EDITOR



This week, we take a little economic theory to the technology space, looking at the technology "bubble" in ASIC design and how that affects FPGAs. While FPGAs have benefited from the slowdown in ASIC design starts, the resulting decay of the ASIC ecosystem could ultimately be harmful to FPGA technology as well.



Also new this week, we have a contributed article from Auspy and Mentor Graphics about multi-FPGA partitioning for prototyping work. When the size of your design is more than a single FPGA can handle, you have to partition your prototype across multiple devices. This article explains how to deal with some of the complexity of that operation.

Thanks for reading! If there's anything we can do to make our publications more useful to you, please let us know at:comments (AT) fpgajournal (DOT) com. If you'd rather sound off in public, please post your comments or questions in our Journal Forums.



Kevin Morris – Editor in Chief
Techfocus Media, Inc.











EVENTS & ANNOUNCEMENTS












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LATEST NEWS



March 10, 2009



CebaTech Takes Intellectual Property Business to the Next Level with CebaRIP Rapidly Tunable Cores



Synopsys DesignWare USB 2.0 nanoPHY and PCI Express 1.1 PHY IP First to Achieve Compliance in UMC's 65-Nanometer Process Technologies



March 9, 2009



Actel’s New Fusion Embedded Development Kit Showcases Unique Mixed-Signal FPGA Design Capabilities



Tundra Semiconductor Selects Synopsys as Its Primary EDA Partner



Altera's Stratix IV FPGAs Named Product of the Year by Electronic Products China



Mentor Graphics Precision Synthesis Tool Family Supports Altera’s Stratix IV GT and Arria II GX FPGA Devices



IAR Systems Announces Free IAR Embedded Workbench Development Environment for LEGO® MINDSTORMS®



March 6, 2009



EDA Tech Forum Worldwide Event Series Begins March 26, 2009



March 5, 2009



ARM Cortex-M1 Embedded Processor Design Flow for Actel Nonvolatile FPGAs



Synopsys DesignWare IP for PCI Express First IP to Pass Agilent Technologies' Inline Error Injection Testing



March 4, 2009



Wind River to Offer Linux Support for Altera's Nios II Embedded Processor










CURRENT FEATURE ARTICLES



FPGAs and the IC Bubble
The Techonomics of Programmability
(Kevin Morris)
A Synthesis & Partitioning Strategy for Effective Multi-FPGA Prototyping
by Nang-Ping Chen, Auspy, Inc. and Ehab Mohsen, Mentor Graphics
Simplifying DDR
Mentor’s New DDR Wizard (Bryon Moyer)
Free Linux Microprocessor*
(Some Restrictions Apply)
(Jim Turley)
Lattice Strikes Back
Low-cost, Low-power with SerDes - New ECP3
(Kevin Morris)
Mind the Gap
Taray Bridges Boards and FPGAs (Kevin Morris)
Serial Soirée
Altera Tempts with Tons of Transceivers
(Kevin Morris)





JOURNAL WEBCASTS



CHALK TALK Confirma™: The Next Era Of Prototyping. Struggling with FPGA prototyping boards? Join Amelia Dalton as she talks with Juergen Jaeger of Synopsys about the Next Era of Rapid Prototyping. (Synopsys)

CHALK TALK From Desktop to Target: What You Need From A Development Suite. Is embedded software development and debug a challenge for your team? Join Amelia Dalton as she chats with Jit Sivalogan of Mentor Graphics about setting up a productive environment for embedded development. (Mentor Graphics)

CHALK TALK Simplified Verification of DSP Algorithms in Hardware. Moving algorithms from MATLAB to FPGAs? Join Amelia Dalton as she explores options for verifying DSP designs implemented in FPGAs with Tim Vanevenhoven from Xilinx. (Xilinx)

CHALK TALK Using Embedded Hypervisors in Mobile Devices. Join Amelia Dalton as she explores the use of embedded hypervisors to create safe and secure software for mobile devices with Rob McCammon of Open Kernel Labs. (Open Kernel Labs)



[click here for more webcasts]












FPGAs and the IC Bubble
The Techonomics of Programmability
(Kevin Morris)

Exponentials are exciting!

Anything in the real world that follows an exponential curve is a recipe for increased adrenalin production.  If we're bopping along in our normal linear lives, and we bump into a geometric progression, we (those of us that took math, anyway) naturally expect that we're in for a short and exciting ride.  Something that happens in twos or fours today will be exploding into the 128s and 256s by the end of the week, and next month will be flaming out in the bazillions.  Although these events can have huge amplitudes, their short duration typically prevents the integral from amounting to much, and their lasting effect is minimal.

What the heck was that last paragraph talking about?

Let's come back from the arena of abstract arithmetic for a bit and drop into the real world.  Your e-mail box catches a less-than-funny forward from one of those "forwarding friends," (the type that sends you about twelve uninteresting e-things each day - ranging from virus alerts to chain letters to pictures of political candidates with farm animals photoshopped to their heads.)  If you're early in the wave, you may see the e-joke only once this week.  Next week, however, you'll get three copies - the week after, maybe sixty - and the week after that they'll fill your spam bucket as the exponential explosion of forwards gets the joke to every man, woman, and child in the world with more bandwidth than reading time.  By the fourth week, the joke is gone completely, flamed out in a fiery flash of fuel deprivation.  The world - largely unchanged from the event. [more]







A Synthesis & Partitioning Strategy for Effective Multi-FPGA Prototyping
by Nang-Ping Chen, Auspy, Inc. and Ehab Mohsen, Mentor Graphics

Introduction
Prototyping an ASIC, ASSP, or SoC onto a single FPGA is not without its challenges. You have to deal with differences in ASIC and FPGA architectures, optimize for performance and area requirements, and account for a debug strategy. Unfortunately, this is only the tip of the  iceberg when tasked with implementing an ASIC onto a multi-FPGA platform. Currently, the largest FPGAs have a capacity of roughly 1.5 M equivalent ASIC gates, so when prototyping a chip larger than this, a multi-FPGA strategy must be in place, and several more pitfalls must be accounted for.

And yet it is well worth the effort. Over the years, FPGA prototyping has proven indispensable for functional verification and early software integration. With mask costs approaching $3M for 45nm designs, avoiding a re-spin by prototyping with FPGAs is a small price to pay—even if it means a minor deviation from the final ASIC environment (e.g., clocking, memories, and speed). The larger the design, the more development and manufacturing cost. These larger designs must be partitioned into several FPGAs if they are to be prototyped. It comes as no surprise that for multi-FPGA prototyping, a little pre-planning can go a long way. [more]






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