FPGA Central

FPGA Journal Update




a techfocus media publication :: March 3, 2009 :: volume XXII, no. 09











FROM THE EDITOR



With FPGAs rapidly becoming a platform-of-choice for embedded systems developers, new issues are creeping into our once-simple FPGA design sphere. This week, we have two new features that highlight these challenges. First, Bryon Moyer tells us about generating DDR memory interfaces for connecting your FPGA to external RAM. Next, Jim Turley looks at the recent announcement that Wind River Linux will be running on Altera's NIOS II soft-core processor.

Thanks for reading! If there's anything we can do to make our publications more useful to you, please let us know at:
comments (AT) fpgajournal (DOT) com. If you'd rather sound off in public, please post your comments or questions in our Journal Forums.



Kevin Morris – Editor in Chief
Techfocus Media, Inc.











EVENTS & ANNOUNCEMENTS











Introducing Arria II GX FPGAs. Arria® II GX FPGAs are the lowest power FPGAs with 3.75-Gbps transceivers. Designed for cost-sensitive applications, Arria II GX FPGAs are based on a 40-nm full-featured FPGA fabric and offer improvements in usability that allow you to complete your projects faster.
View the Arria II GX webcast to learn more.




















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LATEST NEWS



March 3, 2009



Agilent Technologies Introduces 100-MHz Oscilloscopes with Largest Display, Mixed-Signal Capability



Curtiss-Wright Controls Announces Its High Sampling Rate Dual-Channel ADC FMC Card for Rugged DSP Applications



Avnet Electronics Marketing Releases New Xilinx Spartan-3A DSP 1800A Video Kit and NEC 6.5 inch LCD Panel Kit



Xilinx Adds Two Authorized Training Providers in North America



March 2, 2009



Sundance Extends PXI Express Product Line with Dual ADC board which offers 2.4Gsps update rate



Altera Selects Altos’ Liberate for Ultra-Fast Characterization of 40nm HardCopy ASICs



National Instruments Announces New Suite of Prototyping Hardware to Lower Development Time and Costs



Atmel Launches Ultra Wideband Evaluation Kit for CAP Customizable Microcontroller



Mentor Graphics Olympus P&R and Calibre Verification Platforms Qualified for 32nm IC Designs at STMi



LatticeECP2M FPGA Enables on Low Cost PCI Express Bridge For VOIP Platforms Based on Intel® Architecture



Embedded World 2009



February 26, 2009



Atmel's Low-cost CAP Starter Kit Hosts Image Viewer Reference Design From PGC



Atmel Launches 2 Million Gate Development Kit for the AT91CAP9H Customizable Microcontroller



Synopsys Enhances DesignWare DDR PHY IP with Service to Verify Signal Integrity



DSP and Microprocessor Algorithms Refactored for FPGA Acceleration



BittWare Adopts VITA 57 FPGA Mezzanine Card Standard



Perfectus Announces Industry’s First SystemVerilog-Based OVM Compliant SuperSpeed USB Verification IP for USB 3.0 Protocol



February 25, 2009



National Instruments Introduces Industry's First 3U Quad-Core PXI Controller



Xilinx at Embedded World 2009



Faster ARM Cortex-M3 Processor Debugging with New Release of IAR Embedded Workbench










CURRENT FEATURE ARTICLES



Simplifying DDR
Mentor’s New DDR Wizard (Bryon Moyer)
Free Linux Microprocessor*
(Some Restrictions Apply)
(Jim Turley)
Lattice Strikes Back
Low-cost, Low-power with SerDes - New ECP3
(Kevin Morris)
Mind the Gap
Taray Bridges Boards and FPGAs (Kevin Morris)
Serial Soirée
Altera Tempts with Tons of Transceivers
(Kevin Morris)
Grand Unification Theory
Xilinx Launches 40/45nm Virtex-6/Spartan-6
(Kevin Morris)





JOURNAL WEBCASTS



CHALK TALK Confirma™: The Next Era Of Prototyping. Struggling with FPGA prototyping boards? Join Amelia Dalton as she talks with Juergen Jaeger of Synopsys about the Next Era of Rapid Prototyping. (Synopsys)

CHALK TALK From Desktop to Target: What You Need From A Development Suite. Is embedded software development and debug a challenge for your team? Join Amelia Dalton as she chats with Jit Sivalogan of Mentor Graphics about setting up a productive environment for embedded development. (Mentor Graphics)

CHALK TALK Simplified Verification of DSP Algorithms in Hardware. Moving algorithms from MATLAB to FPGAs? Join Amelia Dalton as she explores options for verifying DSP designs implemented in FPGAs with Tim Vanevenhoven from Xilinx. (Xilinx)

CHALK TALK Using Embedded Hypervisors in Mobile Devices. Join Amelia Dalton as she explores the use of embedded hypervisors to create safe and secure software for mobile devices with Rob McCammon of Open Kernel Labs. (Open Kernel Labs)

Introducing Actel nano FPGAs. Actel® nano FPGAs go where no FPGA has gone before. With nanoPower, nanoSize, nanoLead-times, nanoTemp, and nanoPrice, IGLOO® nano and ProASIC®3 nano FPGAs bring flashbased advantages to the highvolume, small form factor, portableelectronic device market. View the webcast to learn more. (Actel)

CHALK TALK Catapult C Synthesis Designing a JPEG Compression Engine. Amelia Dalton finds out that designing hardware with high-level languages can be both easy and fun as she and Stuart Clubb of Mentor Graphics walk you through the design of a hardware JPEG encoder using C++. (Mentor Graphics)



[click here for more webcasts]












Simplifying DDR
Mentor’s New DDR Wizard
(Bryon Moyer)

Over in one of our sister pubs, we did a review of some of the challenges of DDR last year. In particular, DDR3 has some incredible timing subtleties that have to be managed. DDR controllers are available as IP for FPGAs, but they still have to be connected to the memories on the board. And those board connections can seriously affect whether or not the timing requirements of the DDR protocols are properly met.

Mentor has just announced new versions of their HyperLynx PI and SI board power integrity products, and the SI one has a briefly-mentioned little feature that I got to see in action at DesignCon; apparently they’re finding that this “oh and by the way” thing is much more than a trivial add-on. It’s a wizard that allows you to specify how you’ve configured your DDR controller and then check out whether the timing passes muster. It can handle DDR, DDR2, and DDR3. A lot of the popularity seems to be with FPGA applications (although it can be used with other controllers as well). Granted, this is a board design tool, but this is where board meets FPGA. [more]







Free Linux Microprocessor*
(Some Restrictions Apply)
(Jim Turley)

In keeping with our theme of free stuff (see Embedded Technology Journal, January 27, 2009) we proudly chronicle the newest free alternative for embedded developers: a free Linux-compatible microprocessor. Never has so much been offered to so many for so little. Or something like that.

Here’s the deal. Altera, the world’s second-best-known FPGA company, has struck a deal with Wind River Systems, the world’s second-best-known embedded-software company, to port Linux to Altera’s NIOS II processor. And since NIOS is free, you’ve got yourself a free 32-bit microprocessor capable of running a genuine full-on multitasking Linux operating system.

Naturally, there’s a catch. In fact, there are two. First off, NIOS is free only if you’re already using Altera’s FPGA chips (more on this later). Second, the Linux itself isn’t free; Wind River charges a significant amount of money for access to the software, and even more money for annual support. [more]






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