FPGA Central

Hello

Depending on your product, you may find the ASICs are the
way to go but you use FPGAs for prototyping. What happens
when your ASIC cannot fit into a single FPGA? As with any
verification methodology, you want a flow that offers
automation and flexibility. Want to learn more? Check out
our paper on ASIC prototyping with multiple FPGAs.

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IN THIS ISSUE:

> Technical Publication
> On-Demand Web Seminars
> Online Product Demos
> Evaluation Software
> Partner Events

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> Technical Publication

* Designing Multi-FPGA Prototypes That Act Like ASICs
FPGA prototyping has become indispensable for
functional verification and early software integration
of prospective ASIC designs. If the ASIC in question is
large, it is often necessary to spread the
functionality across multiple FPGAs on a special
prototype board. This white paper discusses the
importance of choosing the right tools and methods to
most efficiently partition ASIC functions into multiple
FPGAs for development and evaluation purposes.
http://lyris.mentor-info.com/t/10542...29/12078/3427/

> On-Demand Web Seminars

* Automating Requirements Traceability

Learn how to provide detailed requirements tracing
into design source and verification results to
demonstrate a verified implementation for regulatory
compliance.

View now
http://lyris.mentor-info.com/t/10542...29/12081/3428/

* Automating Design Checking to Ensure Consistent RTL
Quality

Development projects need a level of predictability
and automation to support efficient process, in this
session a practical approach to ensure RTL code quality
consistency is demonstrated, along with coding
recommendations for downstream synthesis and simulation
success.

View now
http://lyris.mentor-info.com/t/10542...29/12082/3429/

* Accelerating RTL Reuse

Managing complex development projects that include
blocks from previous designs can impact the schedule in
unforeseen ways. This session will offer guidelines for
code reuse and how to apply some practical approaches
to accelerate the effort.

View now
http://lyris.mentor-info.com/t/10542...29/12081/3428/

> Online Product Demos

* SystemVerilog for FPGA Design with Precision Synthesis
Learn how SystemVerilog helps FPGA designers code at
higher levels of abstraction and for better
verification. Using a sample design, this brief demo
presents the benefits of SystemVerilog's design
features and Precision's extensive support of the
various language constructs.
http://lyris.mentor-info.com/t/10542...29/12083/2735/

* Precision RTL Plus
Precision RTL Plus offers an improved way of designing
FPGAs and dramatically increases designer productivity
by providing several industry-first capabilities that
enable every designer, regardless of level of
expertise, to reach timing closure faster, minimize the
impact of late cycle design changes, and make efficient
use of FPGA architectural blocks.
http://lyris.mentor-info.com/t/10542...29/12083/2735/

* RTL Reuse Methodology
Too often, designers spend excessive time trying to
decipher code structure, interface requirements, naming
conventions, basic functional behavior, resolve
environmental issues, and even chase hard to find bugs.
View these multimedia demos to learn how to save time
and effort reusing legacy code.
http://lyris.mentor-info.com/t/10542...29/12084/1552/

> Evaluation Software

* Precision RTL Plus

The Precision 2009a release focuses on enhanced
capacity to synthesize large designs, improved
usability, and better tool flow integration. Several
new features include 64-bit application support on
Linux for increased capacity, a new constraint viewer
for better design analysis, Altera Stratix-IV physical
synthesis for improved QoR, I/O driven physical
synthesis for an improved FPGA-to-PCB flow, and
improved integration with Mathworks Simulink HDLCoder
and FormalPro equivalence checker.

Request an evaluation license for Precision®
Synthesis
http://lyris.mentor-info.com/t/10542...29/12085/2552/

> Partner Events

* Verification Academy - Now Available!

Verification Academy is a series of online courses
that provides the methodological bridge to help you
move from the high-level value propositions of advanced
verification to the nuts-and-bolts of how to actually
deploy these technologies.

Current Course Modules:

- Assertion Based Verification
- Clock Domain Crossing

More information and registration
http://lyris.mentor-info.com/t/10542...29/12086/3346/

Have a friend or colleague that would like this
newsletter?
Feel free to pass it on!

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Simon Bloch
Vice President and General Manager, DCS Division

Mentor Graphics Corporation
http://lyris.mentor-info.com/t/10542...29/12087/2736/
Email: fpga_news (AT) mentor (DOT) com

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