FPGA Central

Hello

Is your product running behind? Are the deadlines a
perpetual trauma? Learn how making changes in the design
process can save loads of time before your code breaks your
back; just check out our tech pub. If you have other design
issues, try the Mentor Graphics Communities
(http://lyris.mentor-info.com/t/10777.../12216/2837/): a technical forum where
engineers can learn, share and network with each other.

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IN THIS ISSUE:

> Technical Publication
> On-Demand Web Seminars
> Online Product Demos
> Evaluation Software

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> Technical Publication

* Avoid FPGA Project Delays by Adopting Advanced Design
Methodologies
Over 40% of FPGA design projects fall behind schedule.
In order to reduce risk of delay of product delivery,
changes need to be made not just in verification but
also in the design process itself. Design
simplification must be a principle that starts at the
beginning of the project life cycle - before
verification of complex code has become the bottleneck
that delays project delivery.
http://lyris.mentor-info.com/t/10777...29/12217/3464/

> On-Demand Web Seminars

* Making the Right Architectural Decisions

Understanding what your system really needs to do
before you build it is fundamental to success in
developing today's complex systems. In this session we
walk through an architectural design example to learn
the value of doing system level analysis. Taking into
consideration the decisions that need to be made
related to hardware and software partitioning,
processor selection, interconnect and memory
hierarchies, fabric infrastructures and caching
strategies will have dramatic effects on the RTL.

View now
http://lyris.mentor-info.com/t/10777...29/12218/3436/

* Automating Requirements Traceability

Learn how to provide detailed requirements tracing
into design source and verification results to
demonstrate a verified implementation for regulatory
compliance.

View now
http://lyris.mentor-info.com/t/10777...29/12219/3465/

* Automating Design Checking to Ensure Consistent RTL
Quality

Development projects need a level of predictability
and automation to support efficient process, in this
session a practical approach to ensure RTL code quality
consistency is demonstrated, along with coding
recommendations for downstream synthesis and simulation
success.

View now
http://lyris.mentor-info.com/t/10777...29/12220/3429/

* Accelerating RTL Reuse

Managing complex development projects that include
blocks from previous designs can impact the schedule in
unforeseen ways. This session will offer guidelines for
code reuse and how to apply some practical approaches
to accelerate the effort.

View now
http://lyris.mentor-info.com/t/10777...29/12221/3428/

* What is Intelligent Testbench Automation

The aim of intelligent testbench automation is to find
more design bugs earlier in the verification process.
This webinar discusses the methods behind Mentor's
intelligent testbench automation tool, inFact. It will
present how to apply different verification strategies
without having to re-write the entire test bench and
how intelligent testbench components fit into your
overall verification architecture.

View now
http://lyris.mentor-info.com/t/10777...29/12222/3466/

> Online Product Demos

* SystemVerilog for FPGA Design with Precision Synthesis
Learn how SystemVerilog helps FPGA designers code at
higher levels of abstraction and for better
verification. Using a sample design, this brief demo
presents the benefits of SystemVerilog's design
features and Precision's extensive support of the
various language constructs.
http://lyris.mentor-info.com/t/10777...29/12223/2735/

* Precision RTL Plus
Precision RTL Plus offers an improved way of designing
FPGAs and dramatically increases designer productivity
by providing several industry-first capabilities that
enable every designer, regardless of level of
expertise, to reach timing closure faster, minimize the
impact of late cycle design changes, and make efficient
use of FPGA architectural blocks.
http://lyris.mentor-info.com/t/10777...29/12223/2735/

* RTL Reuse Methodology
Too often, designers spend excessive time trying to
decipher code structure, interface requirements, naming
conventions, basic functional behavior, resolve
environmental issues, and even chase hard to find bugs.
View these multimedia demos to learn how to save time
and effort reusing legacy code.
http://lyris.mentor-info.com/t/10777...29/12224/1552/

> Evaluation Software

* Precision RTL Plus

The Precision 2009a release focuses on enhanced
capacity to synthesize large designs, improved
usability, and better tool flow integration. Several
new features include 64-bit application support on
Linux for increased capacity, a new constraint viewer
for better design analysis, Altera Stratix-IV physical
synthesis for improved QoR, I/O driven physical
synthesis for an improved FPGA-to-PCB flow, and
improved integration with Mathworks Simulink HDLCoder
and FormalPro equivalence checker.

Request an evaluation license for Precision®
Synthesis
http://lyris.mentor-info.com/t/10777...29/12225/2552/

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Simon Bloch
Vice President and General Manager, DCS Division

Mentor Graphics Corporation
http://lyris.mentor-info.com/t/10777...29/12226/2736/
Email: fpga_news (AT) mentor (DOT) com

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