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Programmable Logic DesignLine Newsletter
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The Programmable Logic DesignLine Newsletter is delivered to you free
of charge from the staff of Programmable Logic DesignLine.
To view the Programmable Logic DesignLine visit:
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11-25-2009

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This issue sponsored by: Avnet

The Xilinx(r) Virtex(r)-6 LX130T Evaluation Kit, designed by Avnet,
provides a complete development platform for designing and verifying
applications based on the Virtex-6 LXT FPGA family. Available with the
Virtex-6 LX130T, the kit enables designers to prototype high-performance
designs with ease, while delivering expandability and customization
through the FMC HPC expansion slot, which provides 168 high-speed,
single-ended and differential user I/O. Learn more:
http://newsletter.designlinenetwork....rT0LOB0HVmU0Ek
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EDITOR'S NOTE

Consider this your lucky day. This week's edition of the Programmable
Logic DesignLine newsletter comes to you a day early so that it won't
force U.S. readers to rearrange Thanksgiving holiday plans.

Speaking of Thanksgiving, (you knew this was coming) PLDL
subscribers have a great deal to be thankful for this week.

First and foremost, we have a wonderful design feature article from
the folks at Pico Computing. This piece describes an FPGA-based
accelerated solution for DNA sequencing and dot plotting. Very
interesting stuff.
http://newsletter.designlinenetwork....rT0LOB0HXJl0Ea

Product announcements this week include a Serial RapidIO 2.1 endpoint
soft IP core for Lattice Semiconductor's ECP3 FPGA family.
http://www.pldesignline.com/products/

In news this week, we've got analyst reaction to last week's downgrade
of the semiconductor sector by BofA Merrill Lynch, plus a piece about
IMEC honoring longtime Xilinx chief Wim Roelandts.
href=http://www.pldesignline.com/news/

Don't forget to check out the Fundamentals of Capacitive Touch Control
course, where Steve Bitton takes you from theory of operation right
through to an evaluation kit demonstration.
http://www.techonline.com/learning/course/218600097

While you're at it, stop by the Fundamentals of High-Speed
Transceivers in FPGAs to get the basics of transceiver operation and
how to work with one on an FPGA.
http://www.techonline.com/learning/course/218600106

FEATURED HOW-TO ARTICLE

--Accelerating Bioinformatics Searching and Dot Plotting Using a
Scalable FPGA Cluster--
This paper presents an FPGA-based accelerated solution for DNA
sequencing and dot plotting. It describes how multiple FPGA devices
can be deployed to create a scalable cluster dedicated to the task of
analyzing large amounts of data, and how this clustered hardware
application can be connected to a software application for
visualization and analysis.
http://newsletter.designlinenetwork....rT0LOB0HXJl0Ea

RECENT HOW-TO ARTICLES OF INTEREST

--High-Speed Board Layout Challenges in FPGA/SDI Sub-Systems --
Many video systems are implemented with feature-rich FPGA and
multi-rate SDI integrated circuits that support high performance
professional video transport over long distances. But FPGAs demand
high density routing with fine trace width while high-speed analog SDI
routing demands impedance matching and signal fidelity. This paper
outlines the layout challenges facing hardware engineers and provides
recommendations for dealing with these challenges.
http://newsletter.designlinenetwork....rT0LOB0HWrT0Ep

--Enable low power design with FPGAs--
Size and power considerations are now often the top priority in many
system designs, but portability and long-lasting power can become
conflicting design requirements. FPGAs seem like the best choice but
warning: not all FPGAs are created equal, especially in portable,
low-power applications.
http://newsletter.designlinenetwork....rT0LOB0HVmJ0EZ

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TOP PRODUCTS

--Lattice announces Serial RapidIO 2.1 endpoint soft IP core for ECP3
family --
Lattice Semiconductor Corp. and partner Praesum Communications
announced the availability of the Serial RapidIO 2.1 endpoint soft IP
core for the LatticeECP3 FPGA family.
http://newsletter.designlinenetwork....rT0LOB0HXJm0Eb

--Xilinx announces EasyPath-6 cost-reduction FPGAs --
Xilinx announced the next generation of its FPGA cost-reduction
product, EasyPath-6.
http://newsletter.designlinenetwork....rT0LOB0HXJn0Ec

--Pin-fin heat sink integrates fan --
Thermal management solutions vendor Cool Innovations is offering a new
line of integrated fansinks composed of a pin-fin heat sink and a fan
that is embedded into the heat sink's pin array.
http://newsletter.designlinenetwork....rT0LOB0HXJo0Ed

TOP NEWS ITEMS

--Eight reasons why IC downgrade was baseless --
Another analyst is upset over a recent downgrade in the semiconductor
sector.
http://newsletter.designlinenetwork....rT0LOB0HXJp0Ee

--IMEC honors Wim Roelandts--
The IMEC research center and the K.U.Leuven University in Leuven,
Belgium, announced it has conferred the degree of doctor honoris causa
on Wim Roelandts, ex-chairman and CEO of programmable logic device
vendor Xilinx Inc. (San Jose, Calif.).
http://newsletter.designlinenetwork....rT0LOB0HXJq0Ef

AVAILABLE COURSES

--High Performance Mixed Signal Validation and Debug Webinar--
In this webinar you will learn how mixed signal oscilloscopes can
speed validation and debug of high performance mixed-signal designs.
Examples applications covered in this webinar include high speed
serial, FPGA, RF and memory systems.
http://newsletter.designlinenetwork....rT0LOB0HWHZ0EF

--ARM Portfolio Expansion with Mike Hames, TI and Warren East, ARM --
Mike Hames, TI senior VP and Warren East, CEO of ARM talk about the
latest expansion to the TI ARM portfolio. With the announcement of 29
new Stellaris ARM microcontrollers and two new Cortex-A8 devices from
the Sitara family of microprocessors, TI offers the industry s
broadest range of ARM technology-based processors offered by a single
supplier.
http://newsletter.designlinenetwork....rT0LOB0HWpT0En

FINAL NOTE
That's all for this week, but don't forget that this newsletter
contains only a subset of what's available on the Programmable Logic
DesignLine website.

~~~~~~~~~~~~~~~~~~~ NOW HIRING ~~~~~~~~~~~~~~~~~~~

Electronics Group Now Hiring 11-24-2009

SEL seeking Business Development Manager in Pullman, WA
http://newsletter.designlinenetwork....rT0LOB0HW2m0EC

SEL seeking Integration / Automation Engineer in Charlotte, NC
http://newsletter.designlinenetwork....rT0LOB0HW2n0ED

ESRI seeking Business Manager - Support Services in Redlands, CA
http://newsletter.designlinenetwork....rT0LOB0HVQB0Ex

Amcor PET Packaging seeking Facilities Engineer in Philadelphia, PA
http://newsletter.designlinenetwork....rT0LOB0HW2o0EE

Mentor Graphics seeking Embedded SW Tele-Sales in San Jose, CA
http://newsletter.designlinenetwork....rT0LOB0HV2R0Ei

For more great jobs, career-related news, features and services,
please visit TechInsights EETimesCareers.
http://newsletter.designlinenetwork....rT0LOB0EfwY0ED
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