FPGA Central

You can order Virtex-5 devices from your distributor now, and he will
offer short delivery times.
Whether the distributor carries these parts on his shelves is entirely
his business decision, but he can always get them for you from Xilinx
at short notice. ("4 to 6 weeks" seems to be the standard answer, but
don't be surprised if it is much faster.)
Available from inventory here at Xilinx are nine part / package
combinations, eighteen if you count the leaded/lead-free versions:

XC5VLX30-1FF(G)324C and -676C
XC5VLX50-1FF(G)324C and -676C and -1153C
XC5VLX85-1FF(G)676C and -1153C
XC5VLX110-1FF(G)676C and -1153C

LX is the logic-oriented sub-family, with BlockRAMs and DSP slices, but
without multi-gigabit transceivers. See the data sheet on the Xilinx
website.
The 30 to 110 is a proportional indicator of logic density (thousands
of "equivalent Logic Cells")
The -1 stands for the slowest speed grade (the only one available this
early)
The FF stands for flip-chip ball-grid array, the one way we package all
Virtex-5 family devices
The G stands for "green" = lead-free packages which are all available
right now.

We have found over the years that small-volume users and consultants
often are the most enthusiastic early adopters, but they may not always
be sure about instant availability.
Now you know !
More parts to come very soon.

Peter Alfke, who has been working on and with these parts for over a
year.

OOPS, I forgot to point out that the part number must have ES at the
end of its name, e.g.
XC5VLX30-1FFG324CES.

ES stands for "Early Silicon". The absence of these two letters would
declare it a "volume production" part (which is not available yet), and
the order would automatically be rejected.
One can never be too precise, especially with computerized order entry.
Peter Alfke


Peter Alfke wrote:
> You can order Virtex-5 devices from your distributor now, and he will
> offer short delivery times.
> Whether the distributor carries these parts on his shelves is entirely
> his business decision, but he can always get them for you from Xilinx
> at short notice. ("4 to 6 weeks" seems to be the standard answer, but
> don't be surprised if it is much faster.)
> Available from inventory here at Xilinx are nine part / package
> combinations, eighteen if you count the leaded/lead-free versions:
>
> XC5VLX30-1FF(G)324C and -676C
> XC5VLX50-1FF(G)324C and -676C and -1153C
> XC5VLX85-1FF(G)676C and -1153C
> XC5VLX110-1FF(G)676C and -1153C
>
> LX is the logic-oriented sub-family, with BlockRAMs and DSP slices, but
> without multi-gigabit transceivers. See the data sheet on the Xilinx
> website.
> The 30 to 110 is a proportional indicator of logic density (thousands
> of "equivalent Logic Cells")
> The -1 stands for the slowest speed grade (the only one available this
> early)
> The FF stands for flip-chip ball-grid array, the one way we package all
> Virtex-5 family devices
> The G stands for "green" = lead-free packages which are all available
> right now.
>
> We have found over the years that small-volume users and consultants
> often are the most enthusiastic early adopters, but they may not always
> be sure about instant availability.
> Now you know !
> More parts to come very soon.
>
> Peter Alfke, who has been working on and with these parts for over a
> year.

Peter Alfke wrote:

> See the data sheet on the Xilinx website.

Why can't we get the errata as simple as the datasheet ?. Seems crucial
for ES devices.

Karl.

Karl,

http://www.xilinx.com/xlnx/xweb/xil_...ondaryNavPick=

How easy is that?

Austin

Austin Lesea schreef:
> http://www.xilinx.com/xlnx/xweb/xil_...ondaryNavPick=
>
> How easy is that?
>
> Austin

Not easy enough. I have to register.

Karl.

Peter Alfke wrote:

> OOPS, I forgot to point out that the part number must have ES at the
> end of its name, e.g.
> XC5VLX30-1FFG324CES.
>
> ES stands for "Early Silicon". The absence of these two letters would
> declare it a "volume production" part (which is not available yet), and
> the order would automatically be rejected.
> One can never be too precise, especially with computerized order entry.
> Peter Alfke
>


I thought "ES" stood for "Engineering Sample"....learn something new
every day...

Alan

Karl,

Does that mean you will not use Virtex 5?

Austin

Austin Lesea wrote:
> Karl,
>
> Does that mean you will not use Virtex 5?

It might sound silly, but sometimes that is all it takes.. (Especially
if the process is not fully automated, but I don't know whether that is
the case here).

Cheers,
Jon

We are only interested in serious designers, not just "tire-kickers".
The registration is not a hurdle if you are serious.

BTW: In this case, the errata are really trivial: a register that must
be reset a special way, a reduced max frequency in synchronous FIFO
mode, a missing optional clock inversion somewhere...

"Early Silicon" is my interpretation of ES. To call it "Engineering
Samples" would be misleading. These are full-quality, fully tested and
characterized parts that work over temperature and voltage ranges.

This is Early Silicon, and any design error (and there often is, since
nobody is perfect the first time around) it is described on an errata
sheet. By definition, every ES device has an errata sheet; at best the
sheet just says: No errata! The errata will be fixed in the production
(non-ES) version. That's why we suggest that you avoid, if you can,
shipping our ES parts in your production equipment. Saves you some
logistic confusion.

We are excited that the Virtex-5 parts came out so clean, and with good
manufacturing yield. That's why I took the unusual (controversial?)
step of advertising availability in this newsgroup.
Maybe I can help to reduce the usual design-in delay, to your and to
our benefit.
Peter Alfke, Xilinx
======================

Jon Beniston wrote:
> Austin Lesea wrote:
> > Karl,
> >
> > Does that mean you will not use Virtex 5?
>
> It might sound silly, but sometimes that is all it takes.. (Especially
> if the process is not fully automated, but I don't know whether that is
> the case here).
>
> Cheers,
> Jon

"Peter Alfke" <[email protected]> wrote:

>You can order Virtex-5 devices from your distributor now, and he will
>offer short delivery times.
>Whether the distributor carries these parts on his shelves is entirely
>his business decision, but he can always get them for you from Xilinx
>at short notice. ("4 to 6 weeks" seems to be the standard answer, but
>don't be surprised if it is much faster.)
>Available from inventory here at Xilinx are nine part / package
>combinations, eighteen if you count the leaded/lead-free versions:
>
>XC5VLX30-1FF(G)324C and -676C
>XC5VLX50-1FF(G)324C and -676C and -1153C
>XC5VLX85-1FF(G)676C and -1153C
>XC5VLX110-1FF(G)676C and -1153C
>
>LX is the logic-oriented sub-family, with BlockRAMs and DSP slices, but
>without multi-gigabit transceivers. See the data sheet on the Xilinx
>website.
>The 30 to 110 is a proportional indicator of logic density (thousands
>of "equivalent Logic Cells")
>The -1 stands for the slowest speed grade (the only one available this
>early)
>The FF stands for flip-chip ball-grid array, the one way we package all
>Virtex-5 family devices
>The G stands for "green" = lead-free packages which are all available
>right now.
>
>We have found over the years that small-volume users and consultants
>often are the most enthusiastic early adopters, but they may not always
>be sure about instant availability.
>Now you know !
>More parts to come very soon.
>
>Peter Alfke, who has been working on and with these parts for over a
>year.

How about some budgetary prices for low volumes? I'm Dutch so my first
question is always: "How much does it cost?".

--
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl

> "Early Silicon" is my interpretation of ES. To call it "Engineering
> Samples" would be misleading. These are full-quality, fully tested and
> characterized parts that work over temperature and voltage ranges.

Utter bullshit. Usually you write very fair replies but this is just
nonsense. I have ES1 and ES4 parts from Xilinx that are only sold as no
refunds, no returns, with major components that do not work. They are
not full quality at all. These particular Virtex 5 parts may be very
good, but it is certainly not true for your entire product range and
people should not be mislead in to believing otherwise.

> This is Early Silicon, and any design error (and there often is, since
> nobody is perfect the first time around) it is described on an errata
> sheet.

Thus not "full-quality"

> Maybe I can help to reduce the usual design-in delay, to your and to
> our benefit.

What can I say, I made the mistake of not delaying design-in of Virtex
4 FX parts and am still paying the price today.

Cheers,
Jon

I wanted to stress that ES parts are tested and reliable. They do not
wear out or slowly go bad on you. The Virtex-4FXES devices had severe
functional and parametric (but not "reliability") problems, as covered
in the errata sheets.
We are all very sorry about this, and we have made sure that the next
generation design is far more robust.
Peter Alfke

Peter Alfke wrote:
> I wanted to stress that ES parts are tested and reliable. They do not
> wear out or slowly go bad on you.

To be fair, I've have no problems with what is isn't listed in the
errata.

Cheers,
Jon

On 21 Sep 2006 13:16:08 -0700, "Jon Beniston" <[email protected]>
wrote:

>> "Early Silicon" is my interpretation of ES. To call it "Engineering
>> Samples" would be misleading. These are full-quality, fully tested and
>> characterized parts that work over temperature and voltage ranges.
>
>Utter bullshit. Usually you write very fair replies but this is just
>nonsense. I have ES1 and ES4 parts from Xilinx that are only sold as no
>refunds, no returns, with major components that do not work. They are
>not full quality at all. These particular Virtex 5 parts may be very
>good, but it is certainly not true for your entire product range and
>people should not be mislead in to believing otherwise.
>
>> This is Early Silicon, and any design error (and there often is, since
>> nobody is perfect the first time around) it is described on an errata
>> sheet.
>
>Thus not "full-quality"
>
>> Maybe I can help to reduce the usual design-in delay, to your and to
>> our benefit.
>
>What can I say, I made the mistake of not delaying design-in of Virtex
>4 FX parts and am still paying the price today.
>
>Cheers,
>Jon

I think some slack needs to be cut for Xilinx here :-) At least they
are clearly labelling their ES parts (be engineering sample or early
silicon) as such. If any of you use an Intel or AMD cpu ;-) go to
their respective web sites and look for the errata on the shipping
products. Intel's latest cpu has tens of erratas some of which will be
fixed in a later stepping. AMD's cpu have around half a dozen which
won't be fixed. Anyone who has done any IC development knows how
difficult it is to get it right but most of us do, ... eventually.

Austin Lesea schreef:
> Karl,
>
> Does that mean you will not use Virtex 5?
>
> Austin

Hi Austin,

If I was an engineer and would like to know about the how and what, an
registration requirement, would make me think twice, yes.

Kind regards,
Karl.

Peter Alfke schrieb:

> You can order Virtex-5 devices from your distributor now, and he will
> offer short delivery times.
[...]
> Peter Alfke, who has been working on and with these parts for over a
> year.

It doesnt help much if Xilinx is ready for Virtex-5 it matter if the
customers are.

I have Virtex-5 on the desk already for over weeks, yes shipped by
Avnet
as normal order and I am looking to buy ML501 board NOW but

1) ML501 doesnt seem to be available from Xilinx or Avnet?
2) Virtex-5 MicroBlaze was supposed to be supported in EDK 8.2 SP2
targetted mid Aug - now looking at Xilinx website the EDK SP2 release
date is slipped to mid Oct.

mid Oct it may again be slipped to Mid Aug?

The reference designs for ML501 are downloadable, but ASFAIK they
requires EDK 8.2 SP2 what is not available, so even it may be possible
to obtain V5 silicon NOW there support for Virtex-5 just isnt there for
the Xilinx customers. And for us who are not Xilinx employees it really
doesnt matter how long Xilinx personell has had fun with latest silicon
-
until both the silicon AND tools are available there is no supprort.
So no matter how ready we may be for Virtex-5, and belive me some
of us really are - we are not really able todo any real work until
tools
support is also made available by Xilinx.

Antti
http://www.microfpga.com
FPGA programming without FPGA vendor tools!

Antti schrieb:

> Peter Alfke schrieb:
>
> > You can order Virtex-5 devices from your distributor now, and he will
> > offer short delivery times.
> [...]
> > Peter Alfke, who has been working on and with these parts for over a
> > year.
>
[my own ***** snipped]
> until both the silicon AND tools are available there is no supprort.
> So no matter how ready we may be for Virtex-5, and belive me some
> of us really are - we are not really able todo any real work until
> tools support is also made available by Xilinx.
>

EDK 8.1 SP1 has Virtex-5 MicroBlaze 5.00.a and 5.00.b in it
it is just labelled as "early access" but its readily available.
there is some minor mess with MPD files like FSL bus is not
supported (eg requires manual edit of the MPD) but otherwise
the Virtex-5 can be targetted ok on EDK 8.1 SP1, eg no need
to wait for SP2

here is the picture of the EDK system with Virtex-5

http://www.microfpga.com/joomla/inde...mart&Itemid=26

Antti

Just to clarify the situation:
Antti had ordered the evaluation board for Virtex-5, and Xilinx has
acknowledged and I suppose has shipped the order on Sept 27.
Now let's see how soon it reaches Antti in Munich, Germany,
(Antti please report to the newsgroup when it arrives.
It should not take weeks, the airplane hasn't that much fuel!)
Also, the present version of EDK already supports that board (with
minor wrinkles).
Let's then listen to the continuation of this story...
Peter
======================
Antti wrote:
> Antti schrieb:
>
> > Peter Alfke schrieb:
> >
> > > You can order Virtex-5 devices from your distributor now, and he will
> > > offer short delivery times.
> > [...]
> > > Peter Alfke, who has been working on and with these parts for over a
> > > year.
> >
> [my own ***** snipped]
> > until both the silicon AND tools are available there is no supprort.
> > So no matter how ready we may be for Virtex-5, and belive me some
> > of us really are - we are not really able todo any real work until
> > tools support is also made available by Xilinx.
> >
>
> EDK 8.1 SP1 has Virtex-5 MicroBlaze 5.00.a and 5.00.b in it
> it is just labelled as "early access" but its readily available.
> there is some minor mess with MPD files like FSL bus is not
> supported (eg requires manual edit of the MPD) but otherwise
> the Virtex-5 can be targetted ok on EDK 8.1 SP1, eg no need
> to wait for SP2
>
> here is the picture of the EDK system with Virtex-5
>
> http://www.microfpga.com/joomla/inde...mart&Itemid=26
>
> Antti

Peter Alfke schrieb:
> Just to clarify the situation:
> Antti had ordered the evaluation board for Virtex-5, and Xilinx has
> acknowledged and I suppose has shipped the order on Sept 27.
> Now let's see how soon it reaches Antti in Munich, Germany,
> (Antti please report to the newsgroup when it arrives.
> It should not take weeks, the airplane hasn't that much fuel!)
> Also, the present version of EDK already supports that board (with
> minor wrinkles).
> Let's then listen to the continuation of this story...
> Peter
> ======================
> Antti wrote:
> > Antti schrieb:
> >
> > > Peter Alfke schrieb:
> > >
> > > > You can order Virtex-5 devices from your distributor now, and he will
> > > > offer short delivery times.

Hi Peter,

the order code left my hands, but I am not sure when the order was
(or will be) placed. Its beeing processed and I will monitor the
process.

As of availability of Virtex-5 from distrubutors I can confirm that
XC5VLX50--FF676 arrived from Avnet about 3 weeks ago already.

So they are orderable, and have been sent out and reached the
customer(s).

Virtex-5 support in EDK 8.1 SP1 is defenetly there, and Göran was even
so kind and tested out a MicroFpga Virtex-5 bitstream on ML501 board.

It just worked as made - a fresh new Virtex-5 EDK system worked on real
silicon with the first attempt. So it is possible to create Virtex-5
SoC systems with EDK 8.1 SP1 that just work.

Antti

Antti schrieb:

> Peter Alfke schrieb:
> > Just to clarify the situation:
> > Antti had ordered the evaluation board for Virtex-5, and Xilinx has
> > acknowledged and I suppose has shipped the order on Sept 27.
> > Now let's see how soon it reaches Antti in Munich, Germany,
> > (Antti please report to the newsgroup when it arrives.
> > It should not take weeks, the airplane hasn't that much fuel!)
> > Also, the present version of EDK already supports that board (with
> > minor wrinkles).
> > Let's then listen to the continuation of this story...
> > Peter
> > ======================
> > Antti wrote:
> > > Antti schrieb:
> > >
> > > > Peter Alfke schrieb:
> > > >
> > > > > You can order Virtex-5 devices from your distributor now, and he will
> > > > > offer short delivery times.
>
> Hi Peter,
>
> the order code left my hands, but I am not sure when the order was
> (or will be) placed. Its beeing processed and I will monitor the
> process.
>
> As of availability of Virtex-5 from distrubutors I can confirm that
> XC5VLX50--FF676 arrived from Avnet about 3 weeks ago already.
>
> So they are orderable, and have been sent out and reached the
> customer(s).
>
> Virtex-5 support in EDK 8.1 SP1 is defenetly there, and Göran was even
> so kind and tested out a MicroFpga Virtex-5 bitstream on ML501 board.
>
> It just worked as made - a fresh new Virtex-5 EDK system worked on real
> silicon with the first attempt. So it is possible to create Virtex-5
> SoC systems with EDK 8.1 SP1 that just work.
>
> Antti

uups 8.1 above should be 8.2 of course,
Antti

Peter Alfke wrote:
> We are only interested in serious designers, not just "tire-kickers".
> The registration is not a hurdle if you are serious.

This is patently untrue. Choosing the right silicon for a new project
is an immense task. Selecting the micro for even a small job (except in
special cases) requires me to generate a mountain of paperwork. I have
to show a matrix of choices, pro/con points, cost targets, how that
will affect the BOM of the board, expected EMI issues, first-order
approximation of power budget, etc.

A vendor who puts me through 20 minutes of registration (especially on
Xilinx's bouncy servers - here one second, down the next - and
braindead browser requirements "you must be running IE6 from Win XP SP2
and you must have the patches up to 9/1/2005 installed BUT NOTHING
LATER, and you must have all security disabled and some unstated
ActiveX control installed") is going to be kicked into the "too hard"
pile immediately.

Special case exceptions I referred to above are projects that will
reuse a lot of code from an existing device, so the micro choice is
constrained.

Thank you for that info.
I will contact the right people in Xilinx, and will try to streamline
this process.
There is no reason to run potential (or real) customers through such an
agony.
Thanks again.
Peter Alfke, from home.
=============================
[email protected] wrote:
> Peter Alfke wrote:
> > We are only interested in serious designers, not just "tire-kickers".
> > The registration is not a hurdle if you are serious.
>
> This is patently untrue. Choosing the right silicon for a new project
> is an immense task. Selecting the micro for even a small job (except in
> special cases) requires me to generate a mountain of paperwork. I have
> to show a matrix of choices, pro/con points, cost targets, how that
> will affect the BOM of the board, expected EMI issues, first-order
> approximation of power budget, etc.
>
> A vendor who puts me through 20 minutes of registration (especially on
> Xilinx's bouncy servers - here one second, down the next - and
> braindead browser requirements "you must be running IE6 from Win XP SP2
> and you must have the patches up to 9/1/2005 installed BUT NOTHING
> LATER, and you must have all security disabled and some unstated
> ActiveX control installed") is going to be kicked into the "too hard"
> pile immediately.
>
> Special case exceptions I referred to above are projects that will
> reuse a lot of code from an existing device, so the micro choice is
> constrained.

zwsdotcom,

I agree with Peter, it should not be that hard. I use Mozilla, and
mostly Firefox as browsers. And, as long I enable cookies for the
Xilinx site, I have not had any issues. But I believe you that you have
had a bad experience in the past. I trust Peter to look into it.

Austin (on the road - presented at RADECS 2006 in Athens,Greece. Now in
France to look in on our SEU eperimental platforms.

Austin

> Peter Alfke wrote:
>
>>We are only interested in serious designers, not just "tire-kickers".
>>The registration is not a hurdle if you are serious.
>
>
> This is patently untrue. Choosing the right silicon for a new project
> is an immense task. Selecting the micro for even a small job (except in
> special cases) requires me to generate a mountain of paperwork. I have
> to show a matrix of choices, pro/con points, cost targets, how that
> will affect the BOM of the board, expected EMI issues, first-order
> approximation of power budget, etc.
>
> A vendor who puts me through 20 minutes of registration (especially on
> Xilinx's bouncy servers - here one second, down the next - and
> braindead browser requirements "you must be running IE6 from Win XP SP2
> and you must have the patches up to 9/1/2005 installed BUT NOTHING
> LATER, and you must have all security disabled and some unstated
> ActiveX control installed") is going to be kicked into the "too hard"
> pile immediately.
>
> Special case exceptions I referred to above are projects that will
> reuse a lot of code from an existing device, so the micro choice is
> constrained.
>

Austin Lesea wrote:

> I agree with Peter, it should not be that hard. I use Mozilla, and
> mostly Firefox as browsers. And, as long I enable cookies for the

I've never seen anything approaching a reasonable explanation.
xilinx.com simply Does Not Work properly from where I'm sitting. MSIE,
Firefox, Safari on a Mac, Mozilla on a Linux box - NONE of them worked
properly for me.

And results are distinctly varied, as you've seen from the responses in
that thread I posted. People for whom it doesn't work, like me, REALLY
have ENORMOUS trouble getting in. People for whom it "just works" seem
to have no trouble even if they switch to a different browser.

Maybe Xilinx runs some load-balancing system that bounces visitors to
different mirrors according to their geographical location, and maybe
one or more of the mirrors is broken.

All this is a bit moot anyway. Xilinx has no rational reason to make
people jump through these flaming hoops to get basic information about
their parts. If they want people to go with other vendors whose
procedures are less broken, they're going the right way about it.

[email protected] wrote:
> All this is a bit moot anyway. Xilinx has no rational reason to make
> people jump through these flaming hoops to get basic information about
> their parts. If they want people to go with other vendors whose
> procedures are less broken, they're going the right way about it.


Are errata considered at least *slightly* sensitive information? It's
true that people can falsify registration information to get the info,
but those getting the errata (as opposed to the data sheet) should agree
to some specific issues regarding the errata; a good way to track that
the agreement was accepted is with a registration.

While I understand there should be nothing like the experience you've
seen to stand between an engineer and an errata, should this information
be made available without condition? Ar is it just that the hoops
should be simpler?