FPGA Central

Hey,

I made a FSM with about 23 states (not the first time i've done vhdl
work, but never had this problem before with FSM => in fact it is not
really a problem) and i used following scheme:

sequencingrocess(state,...)
begin
case state is
when ... =>
end case;
end process;

updaterocess(reset, clk)
begin
if (reset='1') then
state<=...;
elsif (clk'event and clk='1') then
state<=next_state;
end if;
end process;

logicrocess(clk)
begin
if (clk'event and clk='1') then
...
end if;
end process;

so i don't think it is the way the fsm is build up ... so when i
compile it it does say :

Using one-hot encoding for signal <state>.

but i don't get a f.e.

Found finite state machine <FSM_0> for signal <state>.

-----------------------------------------------------------------------
| States | 3
|
| Transitions | 7
|
| Inputs | 4
|
| Outputs | 3
|
| Clock | clk (rising_edge)
|
| Reset | reset (positive)
|
| Reset type | asynchronous
|
| Reset State | idle
|
| Power Up State | idle
|
| Encoding | automatic
|
| Implementation | LUT
|

-----------------------------------------------------------------------

and i was just wondering why XST does not find my FSM????

thank you in advance,

kind regards,

Tim

oh, and i forgot to mention that it found the FSM in ISE6.1 but not in
ISE7.1 ...

the result:

Found finite state machine <FSM_0> for signal <state>.

-----------------------------------------------------------------------
| States | 23
|
| Transitions | 82
|
| Inputs | 38
|
| Outputs | 28
|
| Clock | clk (rising_edge)
|
| Reset | reset (positive)
|
| Reset type | asynchronous
|
| Reset State | idle_st
|
| Power Up State | idle_st
|
| Encoding | automatic
|
| Implementation | LUT
|

-----------------------------------------------------------------------

Tim Verstraete wrote:

> I made a FSM with about 23 states (not the first time i've done vhdl
> work, but never had this problem before with FSM => in fact it is not
> really a problem) and i used following scheme:
....
> and i was just wondering why XST does not find my FSM????

Perhaps XST is expecting a one or two process format.

But as you said, this is not really a problem if
sims and runs as you expect. A few dubious statistics
are not worth much extra work.

-- Mike Treseler

What fitter is used ?

I had a similar problem (which is not solved yet)
with Synplify.
I used the following attributes as workaround:

SIGNAL ls_ddr_state, next_ls_ddr_state : ddr_state_type;
attribute syn_keep : boolean;
attribute syn_keep of ls_ddr_state : signal is true;
attribute nomerge : boolean;
attribute nomerge of ls_ddr_state : signal is true;

Rgds
André

Mike Treseler schrieb:

> Tim Verstraete wrote:
>
> > I made a FSM with about 23 states (not the first time i've done vhdl
> > work, but never had this problem before with FSM => in fact it is not
> > really a problem) and i used following scheme:
> ...
> > and i was just wondering why XST does not find my FSM????
>
> Perhaps XST is expecting a one or two process format.
>
> But as you said, this is not really a problem if
> sims and runs as you expect. A few dubious statistics
> are not worth much extra work.
>
> -- Mike Treseler

What fitter is used ?

I had a similar problem (which is not solved yet)
with Synplify.
I used the following attributes as workaround:

SIGNAL ls_ddr_state, next_ls_ddr_state : ddr_state_type;
attribute syn_keep : boolean;
attribute syn_keep of ls_ddr_state : signal is true;
attribute nomerge : boolean;
attribute nomerge of ls_ddr_state : signal is true;

Rgds
André

Mike Treseler schrieb:

> Tim Verstraete wrote:
>
> > I made a FSM with about 23 states (not the first time i've done vhdl
> > work, but never had this problem before with FSM => in fact it is not
> > really a problem) and i used following scheme:
> ...
> > and i was just wondering why XST does not find my FSM????
>
> Perhaps XST is expecting a one or two process format.
>
> But as you said, this is not really a problem if
> sims and runs as you expect. A few dubious statistics
> are not worth much extra work.
>
> -- Mike Treseler