FPGA Central

I would like to exchange information on the Xilinx VSK with others
using the kit.

In particular I have the following observations:

A1. The VSK provides no help to people who do not wish to invest in (a)

Matlab, (b) Simulink, (c) ISE 8.1, and (d) an MXE version compatible
with 8.1. VSK assumes that anyone buying VSK will also buy these
packages, or has them already.

A2. Xilinx should state the conditions in A1 clearly where it offers
VSK for sale.

A3. There is one other serious flaw in the VSK and in the VIOBUS in
that they do not allow for the video clock in the VIODC to be passed
down to ML402 --- so far as I understand the documentation. Only the
100 MHz ML402 clock can be passed up to the VIODC. This situation is
not conducive for testing video designs.

A4. Ideally, Xilinx should have sold the VSK with the following

A4.1. Verilog and VHDL code for the VIODC (Video I/O Daughter Card)

to perform the setup for the video encoder and decoder chips.

A4.2. Provision for passing the pixel clock from VIODC to ML402.

A4.3. Some minimal Verilog and VHDL code for the ML402 including a
pass-through module. A user could then replace the pass-through module
with his/her code in a few minutes and have had a fully functional test

system.

As things stand, I think the VSK is quite useless for my purposes.

I am eager to hear from other users.

Arun Kumar

dakkumar schrieb:

> I would like to exchange information on the Xilinx VSK with others
> using the kit.
>
> In particular I have the following observations:
>
> A1. The VSK provides no help to people who do not wish to invest in (a)
>
> Matlab, (b) Simulink, (c) ISE 8.1, and (d) an MXE version compatible
> with 8.1. VSK assumes that anyone buying VSK will also buy these
> packages, or has them already.
>
> A2. Xilinx should state the conditions in A1 clearly where it offers
> VSK for sale.
>
> A3. There is one other serious flaw in the VSK and in the VIOBUS in
> that they do not allow for the video clock in the VIODC to be passed
> down to ML402 --- so far as I understand the documentation. Only the
> 100 MHz ML402 clock can be passed up to the VIODC. This situation is
> not conducive for testing video designs.
>
> A4. Ideally, Xilinx should have sold the VSK with the following
>
> A4.1. Verilog and VHDL code for the VIODC (Video I/O Daughter Card)
>
> to perform the setup for the video encoder and decoder chips.
>
> A4.2. Provision for passing the pixel clock from VIODC to ML402.
>
> A4.3. Some minimal Verilog and VHDL code for the ML402 including a
> pass-through module. A user could then replace the pass-through module
> with his/her code in a few minutes and have had a fully functional test
>
> system.
>
> As things stand, I think the VSK is quite useless for my purposes.
>
> I am eager to hear from other users.
>
> Arun Kumar

as much as I have understood much of the Xilinx "Video" stuff is only
useable for those who make 20kUSD+ upfront investments to buy bunch of
3rd party stuff!

so whatever you want todo you are at your own and have todo almost
everything from scratch.

Antti

dakkumar wrote:

> I would like to exchange information on the Xilinx VSK with others
> using the kit.
>
> In particular I have the following observations:
>
> A1. The VSK provides no help to people who do not wish to invest in (a)
>
> Matlab, (b) Simulink, (c) ISE 8.1, and (d) an MXE version compatible
> with 8.1. VSK assumes that anyone buying VSK will also buy these
> packages, or has them already.
>
> A2. Xilinx should state the conditions in A1 clearly where it offers
> VSK for sale.
>
> A3. There is one other serious flaw in the VSK and in the VIOBUS in
> that they do not allow for the video clock in the VIODC to be passed
> down to ML402 --- so far as I understand the documentation. Only the
> 100 MHz ML402 clock can be passed up to the VIODC. This situation is
> not conducive for testing video designs.
>
> A4. Ideally, Xilinx should have sold the VSK with the following
>
> A4.1. Verilog and VHDL code for the VIODC (Video I/O Daughter Card)
>
> to perform the setup for the video encoder and decoder chips.
>
> A4.2. Provision for passing the pixel clock from VIODC to ML402.
>
> A4.3. Some minimal Verilog and VHDL code for the ML402 including a
> pass-through module. A user could then replace the pass-through module
> with his/her code in a few minutes and have had a fully functional test
>
> system.
>
> As things stand, I think the VSK is quite useless for my purposes.
>
> I am eager to hear from other users.
>
> Arun Kumar
>

Xilinx has targeted the kit toward the easiest development path, which
for someone not already familiar with DSP design is without a doubt to
use system generator, which requires matlab and simulink. However,
although those are recommended by Xilinx, they are NOT required to do a
video design. Where Matlab and Simulink are third party products,
Xilinx can't really distribute them without compensation to Mathworks.
Those are somewhat pricey products, and if you want a bundled package,
I'm sure you could get it....at a cost commeasurate with the cost of
included products.

I agree that it would have been more useful with the skeleton designs
done in VHDL or verilog and included with the package, however seeing
some of the other reference designs, it would probably only be
marginally functional, and probably wouldn't be suitable to your
application without a more or less complete redesign anyway. It is a
case of you get what you pay for.