FPGA Central

Hi,


I am using Xilinx Virtex5 to build a DDR2 SODIMM memory controller. It
is working well at 200MHz while having calibration problems at 300MHz.
after carefully debugging and simulation, I think that Xilinx
calibration algorithm didn't work well for big skews (about 900 ps
between DQS and its associated DQs) at 300MHz.

Anyone has know about Xilinx DDR2 calibration algorithm, please
advise. Thank you.

On Mar 7, 4:34 am, chestnut <adam0...@gmail.com> wrote:
> Hi,
>
> I am using Xilinx Virtex5 to build a DDR2 SODIMM memory controller. It
> is working well at 200MHz while having calibration problems at 300MHz.
> after carefully debugging and simulation, I think that Xilinx
> calibration algorithm didn't work well for big skews (about 900 ps
> between DQS and its associated DQs) at 300MHz.
>
> Anyone has know about Xilinx DDR2 calibration algorithm, please
> advise. Thank you.

I can't get it working even at 200 mhz.. I connected differential
clock of the board to ddr2 (200mhz), I followed instructions contained
in the pdf for writing the state machine for a test, but data I write
in ddr2 is always different from data I read, even I get init_done
signal and read_data_valid signal. Is your design with or without DCM?