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Xilinx Foundation 9.2 vhdl project won't run without executing cleanup project files

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10-17-2007, 07:31 PM

Dan K

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Xilinx Foundation 9.2 vhdl project won't run without executing cleanup project files

Once routed, project won't simulate (ModelSim) unless "cleanup project
files" is executed.

Once simulated, project won't translate, map, ppr, etc until "cleanup
project files" is executed (the only files removed here are a .fdo and a
..wlf file).

Anybody know what could be causing this? Its not a show stopper, but it's
annoying.

Xilinx ISE 9.2i with SP2 on a windows XP PC

Thanks

Dan

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