FPGA Central

Hi all,
I need a 16 words deep FIFO. I'm using the Xilinx FIFO Generator Core.
I chosen an asynchronous FIFO, but I found an odd behaviour. The FIFO
stores only 15 words then the Full Flag goes high.
Is it normal? Why isn't it storing 16 words?

I tried to monitor the number of words in the FIFO so I added the
RD_DATA_COUNT and WR_DATA_COUNT outputs, they should 4 bits wide but
instead they are 2 bits wide, so the count arrives at 3 and then it
stops.
Where is my error?

I'm starting thinking tha in order to have 16 words I have to implement
a 32 words FIFO.

You "chose an asynchronous FIFO" design. Why? Is your design
synchronous, with the same clock for read and write? If so, use the
synchronous design, it is much simpler and easier to understand.
What is the max clock rate? Which Virtex or Spartan family?
Peter Alfke

Peter Alfke wrote:

> You "chose an asynchronous FIFO" design. Why?

I chose the asynchronous one because I need two different clocks for
reading and writing. Clock for write is 128 MHz. clock for read is 32
MHz.

> Which Virtex or Spartan family?

VirtexII, VP50.

This is not an answer to your query but rather a question to you:

How did you include the generated FIFO from Core Generator in your
project? (I am assuming you're using ISE)

Did you have to compile the cores seperately? Or did ISE take care of
it?

If your 32 MHz clock is really derived from, and thus synchronous with,
the 128 MHz, then I would treat this as a synchronous FIFO.
Asynchronous means that you have no idea of, and no control over, the
phase relationship between the two clocks. And asynchronous FIFO
control is far trickier than synchronous, just because of the unknown
and shifting phase relationships, and the associated possible decoding
glitches and even metastability. Synchronism makes all this so much
easier.
Peter Alfke

Robert wrote:
> This is not an answer to your query but rather a question to you:
>
> How did you include the generated FIFO from Core Generator in your
> project? (I am assuming you're using ISE)
>
> Did you have to compile the cores seperately? Or did ISE take care of
> it?

I use ISE7.1. FIFO Generator works exactly like other cores. I just
clicked on "Add new Source...".
When I used ISE6.3 I was not able to get FIFO Generator work, it always
generated empty cores!

Peter Alfke wrote:
> If your 32 MHz clock is really derived from, and thus synchronous with,
> the 128 MHz, then I would treat this as a synchronous FIFO.

In the final design they should be synchronous, I should get them from
a DCM with a 64MHz input. Now I just create them in the testbench.
Anyway I don't think this is the problem, the test I'm performing is
very simple, first I raise the wr_enable, I wait for the FULL signal,
and then I lower the wr_enable and after a little bit of time I raise
the rd_enable.

> Asynchronous means that you have no idea of, and no control over, the
> phase relationship between the two clocks. And asynchronous FIFO
> control is far trickier than synchronous, just because of the unknown
> and shifting phase relationships, and the associated possible decoding
> glitches and even metastability. Synchronism makes all this so much
> easier.

I understand that asynchronous FIFOs are more trickier than synchronous
ones ... but I don't want to use a synchronous FIFO, the clocks
relation is not fixed, their ratio could change in the future.
So I'm just asking, is possible to store 16 words in a 16 words deep
FIFO? Or "Deep N" means that I can only store N-1 words?
Is this problem somehow related to the old asynchronous-fifo core
behaviour? I remember that it let me chose only the length like
7,15,31,63 ... i.e. (2^N)-1.

Nemesis ha scritto:

[...]

> Is this problem somehow related to the old asynchronous-fifo core
> behaviour? I remember that it let me chose only the length like
> 7,15,31,63 ... i.e. (2^N)-1.

OK, I just read carefully the summary screens that appears at the of
the FIFO customization ...
When you chose an asynchronous FIFO it says: "Write Depth:15 Read
Depth:15. Actual FIFO depth differs from specified depth in this
configuration".
So this is a "limit" of the asyncrhonous FIFO.

>So I'm just asking, is possible to store 16 words in a 16 words deep
>FIFO? Or "Deep N" means that I can only store N-1 words?

It's possible, but not simple. Keeping track of 0 to 16 words
in a FIFO requires 17 states. That won't fit in 4 bits.

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Hal Murray wrote:
> >So I'm just asking, is possible to store 16 words in a 16 words deep
> >FIFO? Or "Deep N" means that I can only store N-1 words?
>
> It's possible, but not simple. Keeping track of 0 to 16 words
> in a FIFO requires 17 states. That won't fit in 4 bits.

OK.
Is this true also for synchronous FIFO?
In this case FIFO Generator announce a depth equal to 16