FPGA Central

Hi,

I have a vague memory that Xilinx used to provide excel spreadsheets
that showed the graphical pinout of each FPGA package using coloured
cells to represent each pin.
I couldn't find any reference after much googling and searching of the
Xilinx site. Does anyone have a pointer to these spreadsheets, if
indeed they still (or ever) existed?

Rob

<[email protected]> wrote in message
news:11819[email protected] ups.com...
> Hi,
>
> I have a vague memory that Xilinx used to provide excel spreadsheets
> that showed the graphical pinout of each FPGA package using coloured
> cells to represent each pin.
> I couldn't find any reference after much googling and searching of the
> Xilinx site. Does anyone have a pointer to these spreadsheets, if
> indeed they still (or ever) existed?
>
> Rob
>
Hi Rob,
Try partgen -v device_name at the DOS prompt.
HTH, Syms.

Symon wrote:
> Hi Rob,
> Try partgen -v device_name at the DOS prompt.

Or try Jim Wu's ADEPT:
http://home.comcast.net/~jimwu88/tools/adept/

It has a similar functionality built in. Or maybe it calls partgen and
displays tne result in Excel? Dunno, but very handy tool nevertheless.

--
My email address is only valid until the end of the month.
Try figuring out what the address is going to be after that...

<[email protected]> wrote in message
news:[email protected] ups.com...
> Hi,
>
> I have a vague memory that Xilinx used to provide excel spreadsheets
> that showed the graphical pinout of each FPGA package using coloured
> cells to represent each pin.
> I couldn't find any reference after much googling and searching of the
> Xilinx site. Does anyone have a pointer to these spreadsheets, if
> indeed they still (or ever) existed?
>
> Rob
>

They have an Excel spreadsheet for the Spartan 3 - I Googled "spartan 3
datasheets" and went straight to it - but I could only see ASCII text files
for Virtex 4 e.t.c. Maybe they don't do it for BGA packages.

On Jun 15, 1:54 pm, Sean Durkin <news_ju...@durkin.de> wrote:
> Symon wrote:
> > Hi Rob,
> > Try partgen -v device_name at the DOS prompt.
>
> Or try Jim Wu's ADEPT:http://home.comcast.net/~jimwu88/tools/adept/
>
> It has a similar functionality built in. Or maybe it calls partgen and
> displays tne result in Excel? Dunno, but very handy tool nevertheless.

Yes, ADEPT runs partgen and several other ISE tools in the background.
The goal is to present the information in ways that make more sense to
users.

Cheers,
Jim

On 16 Jun, 23:18, "Andrew Holme" <and...@nospam.com> wrote:
> <rob.dim...@gmail.com> wrote in message
>
> news:[email protected] ups.com...
>
> > Hi,
>
> > I have a vague memory that Xilinx used to provide excel spreadsheets
> > that showed the graphical pinout of each FPGA package using coloured
> > cells to represent each pin.
> > I couldn't find any reference after much googling and searching of the
> > Xilinx site. Does anyone have a pointer to these spreadsheets, if
> > indeed they still (or ever) existed?
>
> > Rob
>
> They have an Excel spreadsheet for the Spartan 3 - I Googled "spartan 3
> datasheets" and went straight to it - but I could only see ASCII text files
> for Virtex 4 e.t.c. Maybe they don't do it for BGA packages.

Historically, the xilinx documentation assumed you wanted a certain
amount of logic and gave you the pinouts for each package for a given
density in each table. This was inherently not usefull, the truth
being that you need a certain amount of IO which dictates the package.
About three years ago I had spent several rediculous hours making sure
I could place different densities of virtex in the same pcb footprint
and posted my irritance here.

The guy responsible for the Spartan documentation emailed me wanting
to know what I thought of the docs he had created for spartan. Turned
out he had created what we all needed. He apologised (in so many
words) that he was not responsible for how the virtex pinouts were
presented.

The virtex documentation these days w.r.t. pinout is much better, but
they are different.

Colin