FPGA Central

I generated a fifo with block rams with two independent clocks and a
symmetric widths and depths. the fifo manual digrams state that with
read enable high the data can be read out of the fifo every clock
cycle.
The wr_en signal is running at a half of the write cycle frequency .i.e
the valid data is present on the input bus every second cycle of write
clock. Now once the data has been written I disable the wr_en . I
enable the read enable and the signal is kept at constant high till the
fifo becomes empty.
I simulated the fifo and it turns out that the fifo ouputs the data
every second cycle with a constant high on the rd_en pin.

Is there something to be tweaked to make it output every clock cycle or
is that the peak performance?

If your clock rate is reasonable, then I suspect incorrect timing
(set-up and hold) between the WE and the write clock, so that you are
actually writing on each clock edge (although you want to write only on
every other one.)
That means you write every word twice, and thus it looks as if the
reading is at half speed.
Peter Alfke, Xilinx
=============
nbg2006@gmail.com wrote:
> I generated a fifo with block rams with two independent clocks and a
> symmetric widths and depths. the fifo manual digrams state that with
> read enable high the data can be read out of the fifo every clock
> cycle.
> The wr_en signal is running at a half of the write cycle frequency .i.e
> the valid data is present on the input bus every second cycle of write
> clock. Now once the data has been written I disable the wr_en . I
> enable the read enable and the signal is kept at constant high till the
> fifo becomes empty.
> I simulated the fifo and it turns out that the fifo ouputs the data
> every second cycle with a constant high on the rd_en pin.
>
> Is there something to be tweaked to make it output every clock cycle or
> is that the peak performance?

Thanks for the reply . I was making the silly mistake of writing the
word twice but now I corrected it .The simulations are proper but when
i writie it onto the fpga and check it using chipscope it gives me
data on every second sample of plb clock instead of every sample. I am
reading the fifo using plb clock but in chipscope pro I see a new data
every second sample which ruins my whole state machine inputs .i.e the
data output of fifo is maintained for 2 cycles inspite of me reading it
every cycle .
I use plb clock for the chipscope pro samples.


Peter Alfke wrote:
> If your clock rate is reasonable, then I suspect incorrect timing
> (set-up and hold) between the WE and the write clock, so that you are
> actually writing on each clock edge (although you want to write only on
> every other one.)
> That means you write every word twice, and thus it looks as if the
> reading is at half speed.
> Peter Alfke, Xilinx
> =============
> nbg2006@gmail.com wrote:
> > I generated a fifo with block rams with two independent clocks and a
> > symmetric widths and depths. the fifo manual digrams state that with
> > read enable high the data can be read out of the fifo every clock
> > cycle.
> > The wr_en signal is running at a half of the write cycle frequency .i.e
> > the valid data is present on the input bus every second cycle of write
> > clock. Now once the data has been written I disable the wr_en . I
> > enable the read enable and the signal is kept at constant high till the
> > fifo becomes empty.
> > I simulated the fifo and it turns out that the fifo ouputs the data
> > every second cycle with a constant high on the rd_en pin.
> >
> > Is there something to be tweaked to make it output every clock cycle or
> > is that the peak performance?

I am sure you are making another "silly mistake".
Just keep debugging it, carefully and methodically...
Peter Alfke
==============
nbg2006@gmail.com wrote:
> Thanks for the reply . I was making the silly mistake of writing the
> word twice but now I corrected it .The simulations are proper but when
> i writie it onto the fpga and check it using chipscope it gives me
> data on every second sample of plb clock instead of every sample. I am
> reading the fifo using plb clock but in chipscope pro I see a new data
> every second sample which ruins my whole state machine inputs .i.e the
> data output of fifo is maintained for 2 cycles inspite of me reading it
> every cycle .
> I use plb clock for the chipscope pro samples.
>
>
> Peter Alfke wrote:
> > If your clock rate is reasonable, then I suspect incorrect timing
> > (set-up and hold) between the WE and the write clock, so that you are
> > actually writing on each clock edge (although you want to write only on
> > every other one.)
> > That means you write every word twice, and thus it looks as if the
> > reading is at half speed.
> > Peter Alfke, Xilinx
> > =============
> > nbg2006@gmail.com wrote:
> > > I generated a fifo with block rams with two independent clocks and a
> > > symmetric widths and depths. the fifo manual digrams state that with
> > > read enable high the data can be read out of the fifo every clock
> > > cycle.
> > > The wr_en signal is running at a half of the write cycle frequency .i.e
> > > the valid data is present on the input bus every second cycle of write
> > > clock. Now once the data has been written I disable the wr_en . I
> > > enable the read enable and the signal is kept at constant high till the
> > > fifo becomes empty.
> > > I simulated the fifo and it turns out that the fifo ouputs the data
> > > every second cycle with a constant high on the rd_en pin.
> > >
> > > Is there something to be tweaked to make it output every clock cycle or
> > > is that the peak performance?