FPGA Central

We are considering a change to the IO standard used for the QDR-II
interface (1.5V HSTL Class 1 instead of 1.8V HSTL Class 1 (1.8V)).
Xilinx has not created any demo boards that use the 1.5V interfaces, but
they claim that it should work fine.

Have any of you completed a Xilinx design that uses the 1.5V interfaces
(for QDR-II) or know of a successful development?

Ray

If is of assistance our Broaddown2 product will allow playing at 1.5V on
most banks. Needs some solder bridges made but it is built in. We can do it
also in a crude fashon on Raggedstone1 on 4 banks. Broaddown4 and Hollybush1
(both showing shortly) will also have some capability as well.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan-3 Development
Board.
http://www.enterpoint.co.uk

"Ray Andraka" <[email protected]> wrote in message
news:kpaHf.45966$bF.17191@dukeread07...
> We are considering a change to the IO standard used for the QDR-II
> interface (1.5V HSTL Class 1 instead of 1.8V HSTL Class 1 (1.8V)). Xilinx
> has not created any demo boards that use the 1.5V interfaces, but they
> claim that it should work fine.
>
> Have any of you completed a Xilinx design that uses the 1.5V interfaces
> (for QDR-II) or know of a successful development?

Ray,

Yes, one of my designs has a QDR with 1.5V HSTL-1 interfacing - no problems.

Rog.

"Ray Andraka" <[email protected]> wrote in message
news:kpaHf.45966$bF.17191@dukeread07...
> We are considering a change to the IO standard used for the QDR-II
> interface (1.5V HSTL Class 1 instead of 1.8V HSTL Class 1 (1.8V)). Xilinx
> has not created any demo boards that use the 1.5V interfaces, but they
> claim that it should work fine.
>
> Have any of you completed a Xilinx design that uses the 1.5V interfaces
> (for QDR-II) or know of a successful development?

Roger wrote:
> Ray,
>
> Yes, one of my designs has a QDR with 1.5V HSTL-1 interfacing - no problems.
>
> Rog.
>
> "Ray Andraka" <[email protected]> wrote in message
> news:kpaHf.45966$bF.17191@dukeread07...
>
>>We are considering a change to the IO standard used for the QDR-II
>>interface (1.5V HSTL Class 1 instead of 1.8V HSTL Class 1 (1.8V)). Xilinx
>>has not created any demo boards that use the 1.5V interfaces, but they
>>claim that it should work fine.
>>
>>Have any of you completed a Xilinx design that uses the 1.5V interfaces
>>(for QDR-II) or know of a successful development?
>
>
>

Thanks, that's what I needed to know. A customer is making a custom
board and wanted to know that the 1.5v HSTL worked before committing to it.

"Ray Andraka" <[email protected]> wrote in message
news:_UpHf.48131$bF.46178@dukeread07...
> Roger wrote:
>> Ray,
>>
>> Yes, one of my designs has a QDR with 1.5V HSTL-1 interfacing - no
>> problems.
>>
>> Rog.
>>
>> "Ray Andraka" <[email protected]> wrote in message
>> news:kpaHf.45966$bF.17191@dukeread07...
>>
>>>We are considering a change to the IO standard used for the QDR-II
>>>interface (1.5V HSTL Class 1 instead of 1.8V HSTL Class 1 (1.8V)). Xilinx
>>>has not created any demo boards that use the 1.5V interfaces, but they
>>>claim that it should work fine.
>>>
>>>Have any of you completed a Xilinx design that uses the 1.5V interfaces
>>>(for QDR-II) or know of a successful development?
>>
>>
>>
>
> Thanks, that's what I needed to know. A customer is making a custom board
> and wanted to know that the 1.5v HSTL worked before committing to it.

I've just got 1 QDR on the board so the connections are simple point to
point. I can't comment on a bus arrangement.

Glad to help.

Rog.

Roger wrote:

> "Ray Andraka" <[email protected]> wrote in message
> news:_UpHf.48131$bF.46178@dukeread07...
>
>>Roger wrote:
>>
>>>Ray,
>>>
>>>Yes, one of my designs has a QDR with 1.5V HSTL-1 interfacing - no
>>>problems.
>>>
>>>Rog.
>>>
>>>"Ray Andraka" <[email protected]> wrote in message
>>>news:kpaHf.45966$bF.17191@dukeread07...
>>>
>>>
>>>>We are considering a change to the IO standard used for the QDR-II
>>>>interface (1.5V HSTL Class 1 instead of 1.8V HSTL Class 1 (1.8V)). Xilinx
>>>>has not created any demo boards that use the 1.5V interfaces, but they
>>>>claim that it should work fine.
>>>>
>>>>Have any of you completed a Xilinx design that uses the 1.5V interfaces
>>>>(for QDR-II) or know of a successful development?
>>>
>>>
>>>
>>Thanks, that's what I needed to know. A customer is making a custom board
>>and wanted to know that the 1.5v HSTL worked before committing to it.
>
>
> I've just got 1 QDR on the board so the connections are simple point to
> point. I can't comment on a bus arrangement.
>
> Glad to help.
>
> Rog.
>
>

Ours has 4 banks, with the banks in pairs so that the address and
control are shared between two devices. Those are clamshell mounted so
that they are pretty close to single source-single destination. If you
have it working with a single device, I think we'll be OK with this.
The customer was concerned with whether or not the 1.5v worked with the
QDR at all or not. Thanks!

Ray,

Running at 200MHz DDR (400M bits) I have noticed that there appears to be
more margin at 1.8V. At 1.5V I start to get bit errors with VCCO under
1.45V, but at 1.8v I can go +/- 5% in my margin tests. This is probably
something specific to my board however (2 QDRs, clamshell mounted).

One other thing I have noticed is that I was hoping to produce one bitfile
which would work at 1.5V or 1.8V HSTL. Sadly, if I instantiate the 1.8V
drivers and run them at 1.5V I get occasional bit errors during ram tests
which I don't if I use the correct drivers. I was a bit surprised as the
input threshold is surely taken from Vref ? Maybe the drive strength or some
other param is altered.

Cheers,
MikeJ