FPGA Central

Xilinx keeps saying LVPECL_2.5 and _3.3V inputs are identical.
Obviously they are NOT. Virtex-II Pro lists only LVPECL_2.5.
LVPECL_3.3 can be found in Virtex-II. Xilinx are saying THEY ARE
IDENTICAL all the time, including in a reply when I asked
specifically. I had to copy/paste the numbers in the data sheets and
pointed out Vih=1.49-2.72 in LVPECL_3.3 is NOT identical to
Vih=0.8-1.2 in LVPECL_2.5, Vil .... When admitted those numbers were
not identical, Xilinx simply just said "go ahead do simulation" and
closed the case.

Now there are two answer records talking about "...because the input
specifications for LVDS_25/33 and LVPECL_25/33 are identical."

Here is the quote from Answer Record # 18095:

"LVDS and LVPECL specifications are available in the "DC and Switching
Characteristics" section of the Spartan-3 data sheet:
http://direct.xilinx.com/bvdocs/publications/ds099-3.pdf"

But Spartan-3 data sheet does not have LVPECL listed in
characteristics section at all.

Can somebody here help to understand all of these things? I am really
confused.

-qlyus

Answer Record # 18095 Spartan-3 - Can I interface a 3.3 volt LVDS or
LVPECL device to a Spartan-3?
Spartan-3 supports only LVDS_25 and LVPECL_25. Can I interface a 3.3
volt LVDS or LVPECL device to a Spartan-3?...
(18130 bytes)

Answer Record # 16830 Virtex-II Pro - Can I put LVDS or LVPECL I/O in
the 3.3V bank?
Virtex-II offers two options for powering LVDS drivers: 2.5V and 3.3V
(both have identical electrical characteristics). Is this possible
with Virtex-II Pro? Can I put LVPECL I/O in the 3.3V bank?...
(25146 bytes)

qlyus,

The Virtex-II DC & Switching Characteristics data sheet mentions that "These
values are valid when driving a 100 ? differential load only" suggesting
that the LVPECL standard is supported for DIFFERENTIAL SIGNALS not the
single ended you appear to be going toward. For a differential signal to
work, both inputs have to be within the receiver's common mode range *and*
have a differential swing at least as high as the receiver's minimum.

If you checked into the Virtex-II user's guide as the Virtex-II data sheet
suggested, the write-up on Using LVPECL I/O in chapter 3 you'll see the
implementation is entirely differential.

If you want to use single-ended LVPECL, you may need to do things a bit
differently and derive your own numbers. Two approaches that *may* work for
a pseudo-LVPECL would be to tie a center-crossing reference to *each*
differential input pair or define the inputs as a reference-based single
input standard with a slighlty different (but very close) center threshold
reference.



"qlyus" <qlyus@yahoo.com> wrote in message
news:da71446f.0402231202.2f8e93ad@posting.google.c om...
> Xilinx keeps saying LVPECL_2.5 and _3.3V inputs are identical.
> Obviously they are NOT. Virtex-II Pro lists only LVPECL_2.5.
> LVPECL_3.3 can be found in Virtex-II. Xilinx are saying THEY ARE
> IDENTICAL all the time, including in a reply when I asked
> specifically. I had to copy/paste the numbers in the data sheets and
> pointed out Vih=1.49-2.72 in LVPECL_3.3 is NOT identical to
> Vih=0.8-1.2 in LVPECL_2.5, Vil .... When admitted those numbers were
> not identical, Xilinx simply just said "go ahead do simulation" and
> closed the case.
>
> Now there are two answer records talking about "...because the input
> specifications for LVDS_25/33 and LVPECL_25/33 are identical."
>
> Here is the quote from Answer Record # 18095:
>
> "LVDS and LVPECL specifications are available in the "DC and Switching
> Characteristics" section of the Spartan-3 data sheet:
> http://direct.xilinx.com/bvdocs/publications/ds099-3.pdf"
>
> But Spartan-3 data sheet does not have LVPECL listed in
> characteristics section at all.
>
> Can somebody here help to understand all of these things? I am really
> confused.
>
> -qlyus
>
> Answer Record # 18095 Spartan-3 - Can I interface a 3.3 volt LVDS or
> LVPECL device to a Spartan-3?
> Spartan-3 supports only LVDS_25 and LVPECL_25. Can I interface a 3.3
> volt LVDS or LVPECL device to a Spartan-3?...
> (18130 bytes)
>
> Answer Record # 16830 Virtex-II Pro - Can I put LVDS or LVPECL I/O in
> the 3.3V bank?
> Virtex-II offers two options for powering LVDS drivers: 2.5V and 3.3V
> (both have identical electrical characteristics). Is this possible
> with Virtex-II Pro? Can I put LVPECL I/O in the 3.3V bank?...
> (25146 bytes)

John_H,

"100 ohm load" does not make difference here because both the tables
for LVPECL_25 in V-II data sheet and the table for LVPECL_33 in V-II
ds have this condition. From the tables, both common mode ranges
*and* diff swings are different each other, as least as I read. I am
talking about Differential *and* Input only. I copied and pasted the
tables as following:

LVPECL DC Specifications (LVPECL_25)
VCCO = 2.5V
VIH 0.8V(min) 2.0V(max)
VIL 0.5V(min) 1.7V(max)
Differential Input Voltage 0.100V(min) -(max)

LVPECL DC Specifications (LVPECL_33)
VCCO = 3.3V
VIH 1.49(min) 2.72V(max)
VIL 0.86(min) 2.125V(max)
Differential Input Voltage 0.3V (min) -(max)

Can you teach how to read their comon mode ranges and diff swings are
same so they are identical?

Thanks.

-qlyus



"John_H" <johnhandwork@mail.com> wrote in message news:<a3u_b.1$tc4.9837@news-west.eli.net>...
> qlyus,
>
> The Virtex-II DC & Switching Characteristics data sheet mentions that "These
> values are valid when driving a 100 ? differential load only" suggesting
> that the LVPECL standard is supported for DIFFERENTIAL SIGNALS not the
> single ended you appear to be going toward. For a differential signal to
> work, both inputs have to be within the receiver's common mode range *and*
> have a differential swing at least as high as the receiver's minimum.
>
> If you checked into the Virtex-II user's guide as the Virtex-II data sheet
> suggested, the write-up on Using LVPECL I/O in chapter 3 you'll see the
> implementation is entirely differential.
>
> If you want to use single-ended LVPECL, you may need to do things a bit
> differently and derive your own numbers. Two approaches that *may* work for
> a pseudo-LVPECL would be to tie a center-crossing reference to *each*
> differential input pair or define the inputs as a reference-based single
> input standard with a slighlty different (but very close) center threshold
> reference.
>
>
>
> "qlyus" <qlyus@yahoo.com> wrote in message
> news:da71446f.0402231202.2f8e93ad@posting.google.c om...
> > Xilinx keeps saying LVPECL_2.5 and _3.3V inputs are identical.
> > Obviously they are NOT. Virtex-II Pro lists only LVPECL_2.5.
> > LVPECL_3.3 can be found in Virtex-II. Xilinx are saying THEY ARE
> > IDENTICAL all the time, including in a reply when I asked
> > specifically. I had to copy/paste the numbers in the data sheets and
> > pointed out Vih=1.49-2.72 in LVPECL_3.3 is NOT identical to
> > Vih=0.8-1.2 in LVPECL_2.5, Vil .... When admitted those numbers were
> > not identical, Xilinx simply just said "go ahead do simulation" and
> > closed the case.
> >
> > Now there are two answer records talking about "...because the input
> > specifications for LVDS_25/33 and LVPECL_25/33 are identical."
> >
> > Here is the quote from Answer Record # 18095:
> >
> > "LVDS and LVPECL specifications are available in the "DC and Switching
> > Characteristics" section of the Spartan-3 data sheet:
> > http://direct.xilinx.com/bvdocs/publications/ds099-3.pdf"
> >
> > But Spartan-3 data sheet does not have LVPECL listed in
> > characteristics section at all.
> >
> > Can somebody here help to understand all of these things? I am really
> > confused.
> >
> > -qlyus
> >
> > Answer Record # 18095 Spartan-3 - Can I interface a 3.3 volt LVDS or
> > LVPECL device to a Spartan-3?
> > Spartan-3 supports only LVDS_25 and LVPECL_25. Can I interface a 3.3
> > volt LVDS or LVPECL device to a Spartan-3?...
> > (18130 bytes)
> >
> > Answer Record # 16830 Virtex-II Pro - Can I put LVDS or LVPECL I/O in
> > the 3.3V bank?
> > Virtex-II offers two options for powering LVDS drivers: 2.5V and 3.3V
> > (both have identical electrical characteristics). Is this possible
> > with Virtex-II Pro? Can I put LVPECL I/O in the 3.3V bank?...
> > (25146 bytes)

qlyus,
I don't know, but I suspect that this is the case:-
1) The differential receivers works over a very large common mode
range. The common mode voltage probably affects the switching speed
though.
2) The receivers work with very small differential voltages, with the
gotcha being that the smaller the differential voltage the slower the
switching.
3) Xilinx only test the parts to the specifications you quote, because
they can't, or it's too expensive to, check all inputs over all common
mode voltages and differential voltages meet all timing for every part
off the production line.

So, it's physically the *same* receiver, it's just only tested at
the two LVPECL (and the LVDS I guess) points you quote.
Good luck, Symsx.