FPGA Central

I used the ISE 9.2 MIG to create a DDR2 mem controller for 267MHz
memory chips, and it included a DCM to generate the 267MHz clock at 0
and 90 degrees, from an external 267MHz input.

In my app, I have a 100MHz external input clock (low jitter), and I
need four internal clocks:
CLK0: 100MHz with zero skew re the input clock
CLK1: 200MHz for IDELAYCTRL
CLK2: 267MHz 0 degrees for DDR2
CLK3: 267MHz 90 degrees for DDR2

It seems that I can generate all of these with one PLL. The V5 User's
Guide UG190 seems to recommend routing CLKFBOUT through a BUFG to
CLKFBIN (fig 3-10). Or I think I could use the CLK0 BUFG output as
the CLKFBIN signal, and save a BUFG by not using CLKFBOUT.

Is there any reason to prefer CLKFBOUT over CLK0 to get zero skew?
Are CLK2 and CLK3 going to be fine for the MIG DDR2 controller? Is
the PLL's 90 degree difference just as accurate as that of a DCM?

Thanks,
Barry

Barry,

Let me see if I can help,

-snip-

> It seems that I can generate all of these with one PLL.

Yes, the clock tile is quite versatile, and often, user's do not realize
than they can provide all of their timing from one tile's outputs, all
at once.

The V5 User's
> Guide UG190 seems to recommend routing CLKFBOUT through a BUFG to
> CLKFBIN (fig 3-10). Or I think I could use the CLK0 BUFG output as
> the CLKFBIN signal, and save a BUFG by not using CLKFBOUT.

BUFG's are all matched, so if phase accuracy is required, use them.
They do use more power than a direct connection, but the clock tree only
"lights up" (powers) the branches of the H-tree that are used, so power
is also carefully managed. If a tool like Plan-Ahead is used, and logic
for a clock domain is kept within a region, lower clocking power is one
of the benefits.

> Is there any reason to prefer CLKFBOUT over CLK0 to get zero skew?

The DCM uses a tapped delay line, with minimum tap sizing as specified
in the datasheet. The PLL uses a conventional VCO. Your choice. The
PLL has virtually no cycle to cycle jitter, and also does filter jitter
on its input. Phase accuracy is dominated by matching resources
(obviously variations in process means there is no such thing as a
perfect match - again see the datasheet).

> Are CLK2 and CLK3 going to be fine for the MIG DDR2 controller? Is
> the PLL's 90 degree difference just as accurate as that of a DCM?

Again, yes. The accuracy is dominated by matched resource mis-match,
and phase detector offset (imperfections in the phase detectors, used by
both the all-digital DCM, and analog PLL).

Hope that helps,

Austin