FPGA Central

I have a TI TLK2501 SERDES connected to a Virtex-5 on an ML507. The V5
is loading the recovered clock signal with an apparent impedance of 50
ohms (measured by the voltage drop across a series resistor). This is
dropping the voltage swing of the signal in half. We have tried a
different input pin with no change. We then added a buffer with no
change. The ucf for that input is:

NET "RX_CLK" LOC = "G15" | IOSTANDARD = LVCMOS25;

This is not happening to any of the other inputs from the SERDES.

Any ideas as to what is going on?

On Wed, 2 Sep 2009 10:43:27 -0700 (PDT), 2G <[email protected]>
wrote:

>I have a TI TLK2501 SERDES connected to a Virtex-5 on an ML507. The V5
>is loading the recovered clock signal with an apparent impedance of 50
>ohms (measured by the voltage drop across a series resistor). This is
>dropping the voltage swing of the signal in half. We have tried a
>different input pin with no change. We then added a buffer with no
>change. The ucf for that input is:
>
>NET "RX_CLK" LOC = "G15" | IOSTANDARD = LVCMOS25;
>
>This is not happening to any of the other inputs from the SERDES.
>
>Any ideas as to what is going on?
>

Did you check the board schematics? This signal seems to be connected
to the CPLD also which might be causing the issue you see.

--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

On Sep 2, 11:10*am, Muzaffer Kal <k...@dspia.com> wrote:
> On Wed, 2 Sep 2009 10:43:27 -0700 (PDT), 2G <soar2mor...@yahoo.com>
> wrote:
>
> >I have a TI TLK2501 SERDES connected to a Virtex-5 on an ML507. The V5
> >is loading the recovered clock signal with an apparent impedance of 50
> >ohms (measured by the voltage drop across a series resistor). This is
> >dropping the voltage swing of the signal in half. We have tried a
> >different input pin with no change. We then added a buffer with no
> >change. The ucf for that input is:
>
> >NET "RX_CLK" LOC = "G15" | IOSTANDARD = LVCMOS25;
>
> >This is not happening to any of the other inputs from the SERDES.
>
> >Any ideas as to what is going on?
>
> Did you check the board schematics? This signal seems to be connected
> to the CPLD also which might be causing the issue you see.
>
> --
> Muzaffer Kal
>
> DSPIA INC.
> ASIC/FPGA Design Services
>
> http://www.dspia.com

Yes, we are aware of that. We previously used AJ32 and had the same
problem. We used it because it was the only global clock input
available (ISE kept complaining about using that input for a clock
source). If need be, we can isolate the CPLD and LED from that line
(we removed the LED and got no change).

We just tried rerouting that signal to the USER_CLK after removing the
oscillator (X1). This greatly improved the signal quality, but
requires a flying wire off of our mezzanine board to make the
connection.

Well,

Every input has to go from somewhere to get to where it needs to be,
and the pcb traces, and the FPGA package are 50 ohm transmission
lines.

Once the signal gets to the IO pin, the receiver is ~ 8pF of
capacitance, with respect to ground.

I have no idea what the drive capability of the driver is.

Have you simulated the signal integrity using the driver chip IBIS
models, the trace lengths, and the termination chip IBIS models?

I suspect that if you do that, you will see immediately that the ML507
doesn't violate the rules of physics, and may provide you with some
insight why the signal amplitude is reduced.

Austin

On Sep 2, 11:49*am, 2G <soar2mor...@yahoo.com> wrote:
> On Sep 2, 11:10*am, Muzaffer Kal <k...@dspia.com> wrote:
>
>
>
>
>
> > On Wed, 2 Sep 2009 10:43:27 -0700 (PDT), 2G <soar2mor...@yahoo.com>
> > wrote:
>
> > >I have a TI TLK2501 SERDES connected to a Virtex-5 on an ML507. The V5
> > >is loading the recovered clock signal with an apparent impedance of 50
> > >ohms (measured by the voltage drop across a series resistor). This is
> > >dropping the voltage swing of the signal in half. We have tried a
> > >different input pin with no change. We then added a buffer with no
> > >change. The ucf for that input is:
>
> > >NET "RX_CLK" LOC = "G15" | IOSTANDARD = LVCMOS25;
>
> > >This is not happening to any of the other inputs from the SERDES.
>
> > >Any ideas as to what is going on?
>
> > Did you check the board schematics? This signal seems to be connected
> > to the CPLD also which might be causing the issue you see.
>
> > --
> > Muzaffer Kal
>
> > DSPIA INC.
> > ASIC/FPGA Design Services
>
> >http://www.dspia.com
>
> Yes, we are aware of that. We previously used AJ32 and had the same
> problem. We used it because it was the only global clock input
> available (ISE kept complaining about using that input for a clock
> source). If need be, we can isolate the CPLD and LED from that line
> (we removed the LED and got no change).
>
> We just tried rerouting that signal to the USER_CLK after removing the
> oscillator (X1). This greatly improved the signal quality, but
> requires a flying wire off of our mezzanine board to make the
> connection.- Hide quoted text -
>
> - Show quoted text -

How are you physically connecting the TLK2501 to the ML507?

Ed McGettigan
--
Xilinx Inc.

On Sep 2, 6:55*pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
> On Sep 2, 11:49*am, 2G <soar2mor...@yahoo.com> wrote:
>
>
>
>
>
> > On Sep 2, 11:10*am, Muzaffer Kal <k...@dspia.com> wrote:
>
> > > On Wed, 2 Sep 2009 10:43:27 -0700 (PDT), 2G <soar2mor...@yahoo.com>
> > > wrote:
>
> > > >I have a TI TLK2501 SERDES connected to a Virtex-5 on an ML507. The V5
> > > >is loading the recovered clock signal with an apparent impedance of 50
> > > >ohms (measured by the voltage drop across a series resistor). This is
> > > >dropping the voltage swing of the signal in half. We have tried a
> > > >different input pin with no change. We then added a buffer with no
> > > >change. The ucf for that input is:
>
> > > >NET "RX_CLK" LOC = "G15" | IOSTANDARD = LVCMOS25;
>
> > > >This is not happening to any of the other inputs from the SERDES.
>
> > > >Any ideas as to what is going on?
>
> > > Did you check the board schematics? This signal seems to be connected
> > > to the CPLD also which might be causing the issue you see.
>
> > > --
> > > Muzaffer Kal
>
> > > DSPIA INC.
> > > ASIC/FPGA Design Services
>
> > >http://www.dspia.com
>
> > Yes, we are aware of that. We previously used AJ32 and had the same
> > problem. We used it because it was the only global clock input
> > available (ISE kept complaining about using that input for a clock
> > source). If need be, we can isolate the CPLD and LED from that line
> > (we removed the LED and got no change).
>
> > We just tried rerouting that signal to the USER_CLK after removing the
> > oscillator (X1). This greatly improved the signal quality, but
> > requires a flying wire off of our mezzanine board to make the
> > connection.- Hide quoted text -
>
> > - Show quoted text -
>
> How are you physically connecting the TLK2501 to the ML507?
>
> Ed McGettigan
> --
> Xilinx Inc.- Hide quoted text -
>
> - Show quoted text -

The TLK2501 is on a mezzanine board that interconnects thru the
expansion headers (J4-7).

On Sep 2, 1:19*pm, austin <aus...@xilinx.com> wrote:
> Well,
>
> Every input has to go from somewhere to get to where it needs to be,
> and the pcb traces, and the FPGA package are 50 ohm transmission
> lines.
>
> Once the signal gets to the IO pin, the receiver is ~ 8pF of
> capacitance, with respect to ground.
>
> I have no idea what the drive capability of the driver is.
>
> Have you simulated the signal integrity using the driver chip IBIS
> models, the trace lengths, and the termination chip IBIS models?
>
> I suspect that if you do that, you will see immediately that the ML507
> doesn't violate the rules of physics, and may provide you with some
> insight why the signal amplitude is reduced.
>
> Austin

I can do that, but why is this excessive loading appearing on just the
clock input and none of the others?

Tom

On Sep 3, 8:47*am, 2G <soar2mor...@yahoo.com> wrote:
> On Sep 2, 6:55*pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
>
>
>
>
>
> > On Sep 2, 11:49*am, 2G <soar2mor...@yahoo.com> wrote:
>
> > > On Sep 2, 11:10*am, Muzaffer Kal <k...@dspia.com> wrote:
>
> > > > On Wed, 2 Sep 2009 10:43:27 -0700 (PDT), 2G <soar2mor...@yahoo.com>
> > > > wrote:
>
> > > > >I have a TI TLK2501 SERDES connected to a Virtex-5 on an ML507. The V5
> > > > >is loading the recovered clock signal with an apparent impedance of 50
> > > > >ohms (measured by the voltage drop across a series resistor). Thisis
> > > > >dropping the voltage swing of the signal in half. We have tried a
> > > > >different input pin with no change. We then added a buffer with no
> > > > >change. The ucf for that input is:
>
> > > > >NET "RX_CLK" LOC = "G15" | IOSTANDARD = LVCMOS25;
>
> > > > >This is not happening to any of the other inputs from the SERDES.
>
> > > > >Any ideas as to what is going on?
>
> > > > Did you check the board schematics? This signal seems to be connected
> > > > to the CPLD also which might be causing the issue you see.
>
> > > > --
> > > > Muzaffer Kal
>
> > > > DSPIA INC.
> > > > ASIC/FPGA Design Services
>
> > > >http://www.dspia.com
>
> > > Yes, we are aware of that. We previously used AJ32 and had the same
> > > problem. We used it because it was the only global clock input
> > > available (ISE kept complaining about using that input for a clock
> > > source). If need be, we can isolate the CPLD and LED from that line
> > > (we removed the LED and got no change).
>
> > > We just tried rerouting that signal to the USER_CLK after removing the
> > > oscillator (X1). This greatly improved the signal quality, but
> > > requires a flying wire off of our mezzanine board to make the
> > > connection.- Hide quoted text -
>
> > > - Show quoted text -
>
> > How are you physically connecting the TLK2501 to the ML507?
>
> > Ed McGettigan
> > --
> > Xilinx Inc.- Hide quoted text -
>
> > - Show quoted text -
>
> The TLK2501 is on a mezzanine board that interconnects thru the
> expansion headers (J4-7).- Hide quoted text -
>
> - Show quoted text -

Looking back at your posts you started out using AJ32, HDR1_46, and
then switched to G15, GPIO_LED_2, and both of these have an issue with
"dropping the voltage in half" for the RX_CLK output from the TLK2501.

AJ32 is in Bank 13 and is connected to the VCCO_EXP supply and is not
GC or CC clock input pin. Did you set the VCCO_EXP supply to 2.5V
using the J20 jumpers? Is AK32, HDR1_48, used on the TLK2501 board?

G15 is in Bank 1 is connected to VCC2V5 this is a GC clock input, but
it is also connected to the input of the CPLD and the signal integrity
will be reduced. Is G16, GPIO_LED_3 used on the TLK2501 board?

Have you verified that the problem isn't on the TLK2501 board?

On Sep 3, 11:42*am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
> On Sep 3, 8:47*am, 2G <soar2mor...@yahoo.com> wrote:
>
>
>
>
>
> > On Sep 2, 6:55*pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
>
> > > On Sep 2, 11:49*am, 2G <soar2mor...@yahoo.com> wrote:
>
> > > > On Sep 2, 11:10*am, Muzaffer Kal <k...@dspia.com> wrote:
>
> > > > > On Wed, 2 Sep 2009 10:43:27 -0700 (PDT), 2G <soar2mor...@yahoo.com>
> > > > > wrote:
>
> > > > > >I have a TI TLK2501 SERDES connected to a Virtex-5 on an ML507. The V5
> > > > > >is loading the recovered clock signal with an apparent impedanceof 50
> > > > > >ohms (measured by the voltage drop across a series resistor). This is
> > > > > >dropping the voltage swing of the signal in half. We have tried a
> > > > > >different input pin with no change. We then added a buffer with no
> > > > > >change. The ucf for that input is:
>
> > > > > >NET "RX_CLK" LOC = "G15" | IOSTANDARD = LVCMOS25;
>
> > > > > >This is not happening to any of the other inputs from the SERDES..
>
> > > > > >Any ideas as to what is going on?
>
> > > > > Did you check the board schematics? This signal seems to be connected
> > > > > to the CPLD also which might be causing the issue you see.
>
> > > > > --
> > > > > Muzaffer Kal
>
> > > > > DSPIA INC.
> > > > > ASIC/FPGA Design Services
>
> > > > >http://www.dspia.com
>
> > > > Yes, we are aware of that. We previously used AJ32 and had the same
> > > > problem. We used it because it was the only global clock input
> > > > available (ISE kept complaining about using that input for a clock
> > > > source). If need be, we can isolate the CPLD and LED from that line
> > > > (we removed the LED and got no change).
>
> > > > We just tried rerouting that signal to the USER_CLK after removing the
> > > > oscillator (X1). This greatly improved the signal quality, but
> > > > requires a flying wire off of our mezzanine board to make the
> > > > connection.- Hide quoted text -
>
> > > > - Show quoted text -
>
> > > How are you physically connecting the TLK2501 to the ML507?
>
> > > Ed McGettigan
> > > --
> > > Xilinx Inc.- Hide quoted text -
>
> > > - Show quoted text -
>
> > The TLK2501 is on a mezzanine board that interconnects thru the
> > expansion headers (J4-7).- Hide quoted text -
>
> > - Show quoted text -
>
> Looking back at your posts you started out using AJ32, HDR1_46, and
> then switched to G15, GPIO_LED_2, and both of these have an issue with
> "dropping the voltage in half" for the RX_CLK output from the TLK2501.
>
> AJ32 is in Bank 13 and is connected to the VCCO_EXP supply and is not
> GC or CC clock input pin. *Did you set the VCCO_EXP supply to 2.5V
> using the J20 jumpers? *Is AK32, HDR1_48, used on the TLK2501 board?
>
> G15 is in Bank *1 is connected to VCC2V5 this is a GC clock input, but
> it is also connected to the input of the CPLD and the signal integrity
> will be reduced. Is G16, GPIO_LED_3 used on the TLK2501 board?
>
> Have you verified that the problem isn't on the TLK2501 board?- Hide quoted text -
>
> - Show quoted text -

Thanks for the reply.

I checked and it was set to 3.3V, so we changed it to 2.5V and got the
same SI problems, but the bit error went away (due no doubt to the
change in threshold levels). The clock signal itself looks terrible:
its low level is raised to 1.32 V (the high level is 2.5 V), with a
0.15 V glitch on the rising edge at the mid point.

AK32 is used for RXD<8>.

We have isolated the clock signal on the TLK2501 board and it looks
fine. We tried using a different input entirely (HDR1_2, H33) and got
the same results.

I generated the IBIS file for this design and noted that the same IO
standard, LVCMOS25_S_2, is used for all inputs from the TLK2501, yet
the SI problem is exclusive to RX_CLK.

The buffer used, an SL74LVC8T245, is capable of sinking 8 mA with a
2.5 V supply while keeping Vol to 0.3 V max. Doing the math, this
implies there is an equivalent pull-up of about 33 ohms on that line!

Tom

On Sep 3, 4:30*pm, 2G <soar2mor...@yahoo.com> wrote:
> On Sep 3, 11:42*am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
>
>
>
>
>
> > On Sep 3, 8:47*am, 2G <soar2mor...@yahoo.com> wrote:
>
> > > On Sep 2, 6:55*pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
>
> > > > On Sep 2, 11:49*am, 2G <soar2mor...@yahoo.com> wrote:
>
> > > > > On Sep 2, 11:10*am, Muzaffer Kal <k...@dspia.com> wrote:
>
> > > > > > On Wed, 2 Sep 2009 10:43:27 -0700 (PDT), 2G <soar2mor...@yahoo.com>
> > > > > > wrote:
>
> > > > > > >I have a TI TLK2501 SERDES connected to a Virtex-5 on an ML507.. The V5
> > > > > > >is loading the recovered clock signal with an apparent impedance of 50
> > > > > > >ohms (measured by the voltage drop across a series resistor). This is
> > > > > > >dropping the voltage swing of the signal in half. We have tried a
> > > > > > >different input pin with no change. We then added a buffer with no
> > > > > > >change. The ucf for that input is:
>
> > > > > > >NET "RX_CLK" LOC = "G15" | IOSTANDARD = LVCMOS25;
>
> > > > > > >This is not happening to any of the other inputs from the SERDES.
>
> > > > > > >Any ideas as to what is going on?
>
> > > > > > Did you check the board schematics? This signal seems to be connected
> > > > > > to the CPLD also which might be causing the issue you see.
>
> > > > > > --
> > > > > > Muzaffer Kal
>
> > > > > > DSPIA INC.
> > > > > > ASIC/FPGA Design Services
>
> > > > > >http://www.dspia.com
>
> > > > > Yes, we are aware of that. We previously used AJ32 and had the same
> > > > > problem. We used it because it was the only global clock input
> > > > > available (ISE kept complaining about using that input for a clock
> > > > > source). If need be, we can isolate the CPLD and LED from that line
> > > > > (we removed the LED and got no change).
>
> > > > > We just tried rerouting that signal to the USER_CLK after removing the
> > > > > oscillator (X1). This greatly improved the signal quality, but
> > > > > requires a flying wire off of our mezzanine board to make the
> > > > > connection.- Hide quoted text -
>
> > > > > - Show quoted text -
>
> > > > How are you physically connecting the TLK2501 to the ML507?
>
> > > > Ed McGettigan
> > > > --
> > > > Xilinx Inc.- Hide quoted text -
>
> > > > - Show quoted text -
>
> > > The TLK2501 is on a mezzanine board that interconnects thru the
> > > expansion headers (J4-7).- Hide quoted text -
>
> > > - Show quoted text -
>
> > Looking back at your posts you started out using AJ32, HDR1_46, and
> > then switched to G15, GPIO_LED_2, and both of these have an issue with
> > "dropping the voltage in half" for the RX_CLK output from the TLK2501.
>
> > AJ32 is in Bank 13 and is connected to the VCCO_EXP supply and is not
> > GC or CC clock input pin. *Did you set the VCCO_EXP supply to 2.5V
> > using the J20 jumpers? *Is AK32, HDR1_48, used on the TLK2501 board?
>
> > G15 is in Bank *1 is connected to VCC2V5 this is a GC clock input, but
> > it is also connected to the input of the CPLD and the signal integrity
> > will be reduced. Is G16, GPIO_LED_3 used on the TLK2501 board?
>
> > Have you verified that the problem isn't on the TLK2501 board?- Hide quoted text -
>
> > - Show quoted text -
>
> Thanks for the reply.
>
> I checked and it was set to 3.3V, so we changed it to 2.5V and got the
> same SI problems, but the bit error went away (due no doubt to the
> change in threshold levels). The clock signal itself looks terrible:
> its low level is raised to 1.32 V (the high level is 2.5 V), with a
> 0.15 V glitch on the rising edge at the mid point.
>
> AK32 is used for RXD<8>.
>
> We have isolated the clock signal on the TLK2501 board and it looks
> fine. We tried using a different input entirely (HDR1_2, H33) and got
> the same results.
>
> I generated the IBIS file for this design and noted that the same IO
> standard, LVCMOS25_S_2, is used for all inputs from the TLK2501, yet
> the SI problem is exclusive to RX_CLK.
>
> The buffer used, an SL74LVC8T245, is capable of sinking 8 mA with a
> 2.5 V supply while keeping Vol to 0.3 V max. Doing the math, this
> implies there is an equivalent pull-up of about 33 ohms on that line!
>
> Tom- Hide quoted text -
>
> - Show quoted text -

What you are seeing should not be happening so something must be
wrong. I ran a check verification on a ML507 and everything is
working as I expect them to work. A couple of things for you to
check.

1) Is this a standard Xilinx ML507 with a FX70T part?
2) Without your module plug in to the ML507 please verify the
following resistance measurements:
Powered-Off
GND to HDR1_46 = 1Mohm
GND to HDR1_48 = 1Mohm
2V5 to HDR1_46 = 1Mohm
2V5 to HDR1_48 = 1Mohm
Powered-on - But not configured
GND to HDR1_46 = 45Mohm
GND to HDR1_48 = 45Mohm
2V5 to HDR1_46 = 25Kohm (weak pullups enabled)
2V5 to HDR1_48 = 25Kohm (weak pullups enabled)
3) With your design loaded in the FX70T verify the following voltage
measurements
HDR1_46 = 0V
HDR1_48 = 0V

If you get similar results as the above then the cause is not from the
ML507 and the problem must be on your TLK2501 module.

Since the RX_CLK is moving between 1.32V and 2.5V this would indicate
that there is strong pullup (33-50ohm according to your posts) to 2.5V
and there isn't anything on the ML507 that should cause this.

Ed McGettigan
--
Xilinx Inc.