FPGA Central

I am using the FIFO Generator in Coregen to generate a FIFO that is
4x32k with Block Ram. I would expect that since the Virtex 5 block
rams are 36 Kbit, this would take up 4 block rams, but Coregen
estimates 8 block rams.

This is significant since I'm designing an interleaver with 8 of the
FIFOs. So I expected to use 8x4=32 (24%) not 8x8=64 (48%) of my SX50s
block ram. I haven't synthesized the design yet. Is Coregen's
estimate correct? Is there a restriction on the 36 Kbit ram usage
that I missed?

Thanks,
Joe

It will depend on the configuration of the din and dout ports to how man
block rams coregen will use. Have a look at the V5 libraries guide to se
how a bram can be configured.

Jon

On Jun 28, 5:56*am, "maxascent" <maxasc...@yahoo.co.uk> wrote:
> It will depend on the configuration of the din and dout ports to how many
> block rams coregen will use. Have a look at the V5 libraries guide to see
> how a bram can be configured.
>
> Jon

It appears that coregen counts the block rams in Virtex 4 block ram
sizes (so it shows double what it really is for a Virtex 5).
The .xrpt output file lists XST_RAMS as 4 as expected. I will verify
in par but I believe this is the source of my confusion.

Joe