FPGA Central

Dear All;

please, I need to use the library of Unisim from Xilinx in my VHDL
code simulated with ModelSim. How can I make the link? I appreciate
your time answering a basic question like that but it is urgent.

Thank you

Mohamed Elnamaky wrote:
> Dear All;
>
> please, I need to use the library of Unisim from Xilinx in my VHDL
> code simulated with ModelSim. How can I make the link? I appreciate
> your time answering a basic question like that but it is urgent.
>
> Thank you

Hi Mohamed

The best solution is to use compxlib program from XilinxISE packet. For
this open windows console and type:

compxlib -help

read examples and descriptions for all options.

This is a example for VirtexIIPro, ModelsimSE, Unisims and Verilog/VHDL.
Compiled libraries will be placed in c:\Xilinx\comp_libs directory.

compxlib -s mti_se -f virtex2p:u -l all -o c:\Xilinx\comp_libs

After compilation, path to Unisims will be added to modelsim.ini file. I
think that's all. I don't have experience with ModelsimXE. By the way,
which version do you have ?

Michal

If you are using PE/LE/SE then:
1, Look up how to use the Xilinx compxlib utility
2, Compile your Unisim library using compxlib (you might want to do Simprim
and XilinxCorelib at the same time)
3 Invoke Modelsim and add a mapping for the unisim library (alternatively
just update your modelsim.ini file)
4 Try again...:-)

Hans.
www.ht-lab.com


"Mohamed Elnamaky" <[email protected]> wrote in message
news:[email protected] om...
> Dear All;
>
> please, I need to use the library of Unisim from Xilinx in my VHDL
> code simulated with ModelSim. How can I make the link? I appreciate
> your time answering a basic question like that but it is urgent.
>
> Thank you

Dear Michal and Hans;
That was greate and I just did what you both told me and I got the
link to Unisim and SimPrim libraries to my Simulator (Modelsim_SE).
Thank you so much. I just used to be an ASIC Designer and that was my
first time dealing with FPGAs, I'm trying to get now all components
that I can use and design cycle that should run between ModelSim,
Leonardo, and Xilinx. If you can give me some directions, I will be
thankful again.

Mohmaed