FPGA Central

Hi,
Are there anyone here that is familiar with signal integrity concepts?
I'm running a trace (TDI for configuration) under a high-speed
signal(horizontal) (66Mhz) vertically. Will this signal (TDI) impose a
signal integrity problem?

PS: i have other fpga configuration signals running horizontally under
a vertical high speed trace?

Thanks.

yy wrote:
> Hi,
> Are there anyone here that is familiar with signal integrity concepts?
> I'm running a trace (TDI for configuration) under a high-speed
> signal(horizontal) (66Mhz) vertically. Will this signal (TDI) impose a
> signal integrity problem?
>
> PS: i have other fpga configuration signals running horizontally under
> a vertical high speed trace?

If the two traces run parallel for any distance on adjacent layers, you
can expect to see two forms of coupling, inductive and capacitive. The
capacitive coupling effects will be much stronger so for adjacent
layers you can ignore inductive coupling. However, this is a very easy
problem to prevent, just don't run adjacent layers in the same
direction! Run traces on layer 1 horizontal and on layer 2 vertical.
Then you only have to worry about traces running parallel on the same
layer which is a whole different problem and is much easier to deal
with.

Traces that run parallel on the same layer have very little capacitive
coupling. The inductive coupling is such that if you maintain close
spacing to a ground or power plane, you will not see significant
effects. So crosstalk is easily dealt with by applying two simple
rules; 1) run signals on adjacent layers in orthogonal directions and
2) maintain a very close spacing between signal layers and ground/power
planes (5 mil is good). Adding a ground trace between the agressor and
victim trace has no effect that does not come from the extra spacing
between the two. If you have a concern, just increase the spacing
between the signals.

Traces that merely cross do not couple enough to cause a problem in
most circuits.