FPGA Central

Hi there,

I want to perform a timing simulation with ModelSim SE5.7e from the output
generated by Quartus II 3.0. So, I add "mydesign.vho" to my modelsim
project and it compiles without any errors or warnings. However, when I try
to load the design for simulation (without *.sdo for now) the following is
printed out:

# Compile of mydesign.vho was successful.
vsim work.mydesign(structure)
# vsim work.mydesign(structure)
# Loading C:/Modeltech_5.7e/win32/../std.standard
# Loading C:/Modeltech_5.7e/win32/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_5.7e/win32/../std.textio(body)
# Loading C:/Modeltech_5.7e/win32/../ieee.vital_timing(body)
# Loading C:/Modeltech_5.7e/win32/../ieee.vital_primitives(body)
# Loading work.atom_pack(body)
# Loading work.apex20ke_components
# Loading C:/Modeltech_5.7e/win32/../ieee.std_logic_arith(body)
# Loading C:/Modeltech_5.7e/win32/../ieee.std_logic_unsigned(body)
# Loading C:/Modeltech_5.7e/win32/../ieee.std_logic_textio(body)
# Loading work.mydesign(structure)
# Loading work.apex20ke_dpram(vital_dpram_atom)
# Loading work.output_delay(v1)
# ** Error: (vsim-7) Failed to open VHDL file "A()" in rb mode.
# No such file or directory. (errno = ENOENT)
# Time: 0 ns Iteration: 0 Instance:
/mydesign/inst6_alpm_instance_adp0_adpram
# ** Fatal: (vsim-7) Failed to open VHDL file "A()" in rb mode.
# No such file or directory. (errno = ENOENT)
# Time: 0 ns Iteration: 0 Process:
/mydesign/inst6_alpm_instance_adp0_adpram/clock File:
C:/quartus/eda/sim_lib/apex20ke_atoms.vhd
# FATAL ERROR while loading design
# Error loading design

Anybody can help?

Regards,
Cornel Arnet

Cornel Arnet wrote:

> # ** Fatal: (vsim-7) Failed to open VHDL file "A()" in rb mode.
> # No such file or directory. (errno = ENOENT)
> # Time: 0 ns Iteration: 0 Process:
> /mydesign/inst6_alpm_instance_adp0_adpram/clock File:
> C:/quartus/eda/sim_lib/apex20ke_atoms.vhd
> # FATAL ERROR while loading design
> # Error loading design
>
> Anybody can help?

Parenthesis are not allowed in a VHDL filename.
Consider siming your source level before gate level.

-- Mike Treseler

Well, there's no file named "A()" ...and I've already done the source level
simulation.

Cornel Arnet

"Mike Treseler" <[email protected]> wrote in message
news:[email protected]..
> Cornel Arnet wrote:
>
> > # ** Fatal: (vsim-7) Failed to open VHDL file "A()" in rb mode.
> > # No such file or directory. (errno = ENOENT)
> > # Time: 0 ns Iteration: 0 Process:
> > /mydesign/inst6_alpm_instance_adp0_adpram/clock File:
> > C:/quartus/eda/sim_lib/apex20ke_atoms.vhd
> > # FATAL ERROR while loading design
> > # Error loading design
> >
> > Anybody can help?
>
> Parenthesis are not allowed in a VHDL filename.
> Consider siming your source level before gate level.
>
> -- Mike Treseler
>