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Technology mapping in edif netlist to adders and multipliers

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07-02-2009, 03:12 PM

tarujab

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Technology mapping in edif netlist to adders and multipliers

Hi guys,

I am working on a project where a need to map a given vhdl code int
adders and multipliers. On generating the edif netlist using synplify,
get the instances in the form of gates. I tried settin
syn_netlist_hierarchy attribute in sdc file, to generate a hierarchica
netlist, but it didnt help.
Is it possible to do it by writing libraries which are used for th
technology mapping.
How can that be done?

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