FPGA Central

Hi,

I am designing a simple ROM in VHDL and following is the code for
it.Xilinx ISE 6.2i doesn't seem to have any issues synthesizing the
design to a Virtex 2 chip(xc2v4000) or translating/mapping/routing the
design(Implementation process).

When I use the test bench created by HDL bencher to see the results,
in Modelsim, a behavioral simulation shows be proper results but a
post translate simulation or anything beyond that like a Post Map or a
Post place and route simulation show a U on all output pins and
Modelsim gives me a number of warnings about "Unbound components"
shown below..

Im stuck at this design phase and would appreciate any help from the
VHDL gurus out there...Heres the code:-

-----------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity inrom is
Port ( en : in std_logic;
clk : in std_logic;
dout : out std_logic_vector( 15 downto 0);
valid : out std_logic; --valid data is present on output when 1
reset : in std_logic
);
end inrom;

architecture rtl of inrom is

type array_rom is array (15 downto 0) of std_logic_vector( 15 downto
0);
signal myarray : array_rom;
signal valid_sig:std_logic;
signal dout_sig : std_logic_vector(15 downto 0);
signal clk2: std_logic;

begin



myarray(0) <= x"0000";
myarray(1) <= x"0000";
myarray(2) <= x"0000";
myarray(3) <= x"003C";
myarray(4) <= x"0000";
myarray(5) <= x"0000";
myarray(6) <= x"0064";
myarray(7) <= x"0000";
myarray(8) <= x"0000";
myarray(9) <= x"000A";
myarray(10) <= x"0000";
myarray(11) <= x"0000";
myarray(12) <= x"003C";
myarray(13) <= x"0000";
myarray(14) <= x"0000";
myarray(15) <= x"0064";

process( reset,clk)
variable romvar:natural range 0 to 15;

begin
if reset = '1' then
dout_sig <= (others=>'0');
valid_sig <='0';
romvar :=0;

elsif (clk'event and clk='1') then
if en='1' then
dout_sig <= myarray (romvar);
valid_sig<='1';
romvar :=romvar + 1;
else
dout_sig <= myarray (romvar);
valid_sig<='0';
end if;
end if;
end process;

dout <= dout_sig;
valid <=valid_sig;
end rtl;
-------------------------------------------------------------------------
Warnings given by Modelsim:

do inromtbw.ndo
# ** Warning: (vlib-34) Library already exists at "work".
###### inrom_translate.vhd(443): );
# WARNING[1]: inrom_translate.vhd(443): No default binding for
component: "x_mux2". (No entity named "x_mux2" was found)
###### inrom_translate.vhd(455): );
# WARNING[1]: inrom_translate.vhd(455): No default binding for
component: "x_ff". (No entity named "x_ff" was found)
###### inrom_translate.vhd(468): );
# WARNING[1]: inrom_translate.vhd(468): No default binding for
component: "x_xor2". (No entity named "x_xor2" was found)
###### inrom_translate.vhd(472): );
# WARNING[1]: inrom_translate.vhd(472): No default binding for
component: "x_zero". (No entity named "x_zero" was found)
###### inrom_translate.vhd(476): );
# WARNING[1]: inrom_translate.vhd(476): No default binding for
component: "x_one". (No entity named "x_one" was found)
###### inrom_translate.vhd(714): );
# WARNING[1]: inrom_translate.vhd(714): No default binding for
component: "x_lut2". (No entity named "x_lut2" was found)
###### inrom_translate.vhd(2994): );
# WARNING[1]: inrom_translate.vhd(2994): No default binding for
component: "x_lut3". (No entity named "x_lut3" was found)
###### inrom_translate.vhd(3128): );
# WARNING[1]: inrom_translate.vhd(3128): No default binding for
component: "x_lut4". (No entity named "x_lut4" was found)
###### inrom_translate.vhd(3203): );
# WARNING[1]: inrom_translate.vhd(3203): No default binding for
component: "x_or2". (No entity named "x_or2" was found)
###### inrom_translate.vhd(3341): );
# WARNING[1]: inrom_translate.vhd(3341): No default binding for
component: "x_tri". (No entity named "x_tri" was found)
###### inrom_translate.vhd(3450): );
# WARNING[1]: inrom_translate.vhd(3450): No default binding for
component: "x_inv". (No entity named "x_inv" was found)
###### inrom_translate.vhd(3533): port map (O => GSR);
# WARNING[1]: inrom_translate.vhd(3533): No default binding for
component: "x_roc". (No entity named "x_roc" was found)
###### inrom_translate.vhd(3535): port map (O => GTS);
# WARNING[1]: inrom_translate.vhd(3535): No default binding for
component: "x_toc". (No entity named "x_toc" was found)
# vsim -lib work -t 1ps inromtbw
# Loading C:/Modeltech_5.7g/win32/../std.standard
# Loading C:/Modeltech_5.7g/win32/../ieee.std_logic_1164(body)
# Loading C:/Modeltech_5.7g/win32/../ieee.std_logic_arith(body)
# Loading C:/Modeltech_5.7g/win32/../std.textio(body)
# Loading C:/Modeltech_5.7g/win32/../ieee.std_logic_textio(body)
# Loading C:/Modeltech_5.7g/win32/../vital2000.vital_timing(body)
# Loading C:\Xilinx6\vhdl\mti_se\simprim.vcomponents
# Loading C:/Modeltech_5.7g/win32/../vital2000.vital_primitives(body)
# Loading C:\Xilinx6\vhdl\mti_se\simprim.vpackage(body)
# Loading work.inromtbw(testbench_arch)
# Loading work.inrom(structure)
# ** Warning: (vsim-3473) Component 'romvar_madd_n0000_inst_cy_5_0' is
not bound.
# Time: 0 ps Iteration: 0 Region: /inromtbw/uut File:
inrom_translate.vhd
# ** Warning: (vsim-3473) Component 'valid_sig_1' is not bound.
# Time: 0 ps Iteration: 0 Region: /inromtbw/uut File:
inrom_translate.vhd
# ** Warning: (vsim-3473) Component 'mmux_n0001_inst_mux_f5_130' is
not bound.


I can not use a Core generated ROM for this design due to some
restrictions I have in my other codes..Sorry for a rather long mail
and thanks in advance for any help!!

Looks like Simprim libraries are missing which includes components like
x_lut2, x_ff etc. Post Ngdbuild or post PAR back annotated simulation files
have these libraries included. Unisim libraries are behavioral models while
Simprim libraries are gate level models. Did you compile these libraries?

This answer record will guide you on doing backannotated simulations.
http://support.xilinx.com/xlnx/xil_a...PagePath=10177

Regards
Vikram

Sridhar Hegde wrote:

> Hi,
>
> I am designing a simple ROM in VHDL and following is the code for
> it.Xilinx ISE 6.2i doesn't seem to have any issues synthesizing the
> design to a Virtex 2 chip(xc2v4000) or translating/mapping/routing the
> design(Implementation process).
>
> When I use the test bench created by HDL bencher to see the results,
> in Modelsim, a behavioral simulation shows be proper results but a
> post translate simulation or anything beyond that like a Post Map or a
> Post place and route simulation show a U on all output pins and
> Modelsim gives me a number of warnings about "Unbound components"
> shown below..
>
> Im stuck at this design phase and would appreciate any help from the
> VHDL gurus out there...Heres the code:-
>
> -----------------------------------------------------------------------
>
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> -- Uncomment the following lines to use the declarations that are
> -- provided for instantiating Xilinx primitive components.
> --library UNISIM;
> --use UNISIM.VComponents.all;
>
> entity inrom is
> Port ( en : in std_logic;
> clk : in std_logic;
> dout : out std_logic_vector( 15 downto 0);
> valid : out std_logic; --valid data is present on output when 1
> reset : in std_logic
> );
> end inrom;
>
> architecture rtl of inrom is
>
> type array_rom is array (15 downto 0) of std_logic_vector( 15 downto
> 0);
> signal myarray : array_rom;
> signal valid_sig:std_logic;
> signal dout_sig : std_logic_vector(15 downto 0);
> signal clk2: std_logic;
>
> begin
>
> myarray(0) <= x"0000";
> myarray(1) <= x"0000";
> myarray(2) <= x"0000";
> myarray(3) <= x"003C";
> myarray(4) <= x"0000";
> myarray(5) <= x"0000";
> myarray(6) <= x"0064";
> myarray(7) <= x"0000";
> myarray(8) <= x"0000";
> myarray(9) <= x"000A";
> myarray(10) <= x"0000";
> myarray(11) <= x"0000";
> myarray(12) <= x"003C";
> myarray(13) <= x"0000";
> myarray(14) <= x"0000";
> myarray(15) <= x"0064";
>
> process( reset,clk)
> variable romvar:natural range 0 to 15;
>
> begin
> if reset = '1' then
> dout_sig <= (others=>'0');
> valid_sig <='0';
> romvar :=0;
>
> elsif (clk'event and clk='1') then
> if en='1' then
> dout_sig <= myarray (romvar);
> valid_sig<='1';
> romvar :=romvar + 1;
> else
> dout_sig <= myarray (romvar);
> valid_sig<='0';
> end if;
> end if;
> end process;
>
> dout <= dout_sig;
> valid <=valid_sig;
> end rtl;
> -------------------------------------------------------------------------
> Warnings given by Modelsim:
>
> do inromtbw.ndo
> # ** Warning: (vlib-34) Library already exists at "work".
> ###### inrom_translate.vhd(443): );
> # WARNING[1]: inrom_translate.vhd(443): No default binding for
> component: "x_mux2". (No entity named "x_mux2" was found)
> ###### inrom_translate.vhd(455): );
> # WARNING[1]: inrom_translate.vhd(455): No default binding for
> component: "x_ff". (No entity named "x_ff" was found)
> ###### inrom_translate.vhd(468): );
> # WARNING[1]: inrom_translate.vhd(468): No default binding for
> component: "x_xor2". (No entity named "x_xor2" was found)
> ###### inrom_translate.vhd(472): );
> # WARNING[1]: inrom_translate.vhd(472): No default binding for
> component: "x_zero". (No entity named "x_zero" was found)
> ###### inrom_translate.vhd(476): );
> # WARNING[1]: inrom_translate.vhd(476): No default binding for
> component: "x_one". (No entity named "x_one" was found)
> ###### inrom_translate.vhd(714): );
> # WARNING[1]: inrom_translate.vhd(714): No default binding for
> component: "x_lut2". (No entity named "x_lut2" was found)
> ###### inrom_translate.vhd(2994): );
> # WARNING[1]: inrom_translate.vhd(2994): No default binding for
> component: "x_lut3". (No entity named "x_lut3" was found)
> ###### inrom_translate.vhd(3128): );
> # WARNING[1]: inrom_translate.vhd(3128): No default binding for
> component: "x_lut4". (No entity named "x_lut4" was found)
> ###### inrom_translate.vhd(3203): );
> # WARNING[1]: inrom_translate.vhd(3203): No default binding for
> component: "x_or2". (No entity named "x_or2" was found)
> ###### inrom_translate.vhd(3341): );
> # WARNING[1]: inrom_translate.vhd(3341): No default binding for
> component: "x_tri". (No entity named "x_tri" was found)
> ###### inrom_translate.vhd(3450): );
> # WARNING[1]: inrom_translate.vhd(3450): No default binding for
> component: "x_inv". (No entity named "x_inv" was found)
> ###### inrom_translate.vhd(3533): port map (O => GSR);
> # WARNING[1]: inrom_translate.vhd(3533): No default binding for
> component: "x_roc". (No entity named "x_roc" was found)
> ###### inrom_translate.vhd(3535): port map (O => GTS);
> # WARNING[1]: inrom_translate.vhd(3535): No default binding for
> component: "x_toc". (No entity named "x_toc" was found)
> # vsim -lib work -t 1ps inromtbw
> # Loading C:/Modeltech_5.7g/win32/../std.standard
> # Loading C:/Modeltech_5.7g/win32/../ieee.std_logic_1164(body)
> # Loading C:/Modeltech_5.7g/win32/../ieee.std_logic_arith(body)
> # Loading C:/Modeltech_5.7g/win32/../std.textio(body)
> # Loading C:/Modeltech_5.7g/win32/../ieee.std_logic_textio(body)
> # Loading C:/Modeltech_5.7g/win32/../vital2000.vital_timing(body)
> # Loading C:\Xilinx6\vhdl\mti_se\simprim.vcomponents
> # Loading C:/Modeltech_5.7g/win32/../vital2000.vital_primitives(body)
> # Loading C:\Xilinx6\vhdl\mti_se\simprim.vpackage(body)
> # Loading work.inromtbw(testbench_arch)
> # Loading work.inrom(structure)
> # ** Warning: (vsim-3473) Component 'romvar_madd_n0000_inst_cy_5_0' is
> not bound.
> # Time: 0 ps Iteration: 0 Region: /inromtbw/uut File:
> inrom_translate.vhd
> # ** Warning: (vsim-3473) Component 'valid_sig_1' is not bound.
> # Time: 0 ps Iteration: 0 Region: /inromtbw/uut File:
> inrom_translate.vhd
> # ** Warning: (vsim-3473) Component 'mmux_n0001_inst_mux_f5_130' is
> not bound.
>
> I can not use a Core generated ROM for this design due to some
> restrictions I have in my other codes..Sorry for a rather long mail
> and thanks in advance for any help!!

Thanks Vikram,

My Modelsim libraries are compiled.I have the
unisim,simprim,XilinxCorelib libraries compiled and they are under the
directory

C:\modeltech5.7g\xilinx_libs\unisim
C:\modeltech5.7g\xilinx_libs\simprim
C:\modeltech5.7g\xilinx_libs\XilinxCoreLib

Earlier the libraries were pointing to Xilinx Libraries and hence I
was seeing those errors.Now I see new errors like...

# ** Error: inrom_translate.vhd(641): Unknown identifier: init.
###### inrom_translate.vhd(653): INIT => '0'
# ** Error: inrom_translate.vhd(653): Unknown identifier: init.
###### inrom_translate.vhd(665): INIT => '0'
# ** Error: inrom_translate.vhd(665): Unknown identifier: init.
###### inrom_translate.vhd(1936): INIT => '0'
# ** Error: inrom_translate.vhd(1936): Unknown identifier: init.
###### inrom_translate.vhd(1948): INIT => '0'
# ** Error: inrom_translate.vhd(3531): Unknown identifier: x_roc
###### inrom_translate.vhd(3533): port map (O => GSR);
# ** Error: inrom_translate.vhd(3533): Unknown component name
###### inrom_translate.vhd(3534): NlwBlockTOC : X_TOC
# ** Error: inrom_translate.vhd(3534): Statement cannot be labeled.
# ** Error: inrom_translate.vhd(3534): Unknown identifier: x_toc
###### inrom_translate.vhd(3535): port map (O => GTS);
# ** Error: inrom_translate.vhd(3535): Unknown component name
###### inrom_translate.vhd(3537): end Structure;
# ** Error: inrom_translate.vhd(3537): VHDL Compiler exiting
# ERROR: C:/Modeltech_5.7g/win32/vcom failed.


Thanks for any ideas/help,

Sridhar





Vikram Pasham <[email protected]> wrote in message news:<[email protected]>...
> Looks like Simprim libraries are missing which includes components like
> x_lut2, x_ff etc. Post Ngdbuild or post PAR back annotated simulation files
> have these libraries included. Unisim libraries are behavioral models while
> Simprim libraries are gate level models. Did you compile these libraries?
>
> This answer record will guide you on doing backannotated simulations.
> http://support.xilinx.com/xlnx/xil_a...PagePath=10177
>
> Regards
> Vikram
>
> Sridhar Hegde wrote:
>
> > Hi,
> >
> > I am designing a simple ROM in VHDL and following is the code for
> > it.Xilinx ISE 6.2i doesn't seem to have any issues synthesizing the
> > design to a Virtex 2 chip(xc2v4000) or translating/mapping/routing the
> > design(Implementation process).
> >
> > When I use the test bench created by HDL bencher to see the results,
> > in Modelsim, a behavioral simulation shows be proper results but a
> > post translate simulation or anything beyond that like a Post Map or a
> > Post place and route simulation show a U on all output pins and
> > Modelsim gives me a number of warnings about "Unbound components"
> > shown below..
> >
> > Im stuck at this design phase and would appreciate any help from the
> > VHDL gurus out there...Heres the code:-
> >
> > -----------------------------------------------------------------------
> >
> > library IEEE;
> > use IEEE.STD_LOGIC_1164.ALL;
> > use IEEE.STD_LOGIC_ARITH.ALL;
> > -- Uncomment the following lines to use the declarations that are
> > -- provided for instantiating Xilinx primitive components.
> > --library UNISIM;
> > --use UNISIM.VComponents.all;
> >
> > entity inrom is
> > Port ( en : in std_logic;
> > clk : in std_logic;
> > dout : out std_logic_vector( 15 downto 0);
> > valid : out std_logic; --valid data is present on output when 1
> > reset : in std_logic
> > );
> > end inrom;
> >
> > architecture rtl of inrom is
> >
> > type array_rom is array (15 downto 0) of std_logic_vector( 15 downto
> > 0);
> > signal myarray : array_rom;
> > signal valid_sig:std_logic;
> > signal dout_sig : std_logic_vector(15 downto 0);
> > signal clk2: std_logic;
> >
> > begin
> >
> > myarray(0) <= x"0000";
> > myarray(1) <= x"0000";
> > myarray(2) <= x"0000";
> > myarray(3) <= x"003C";
> > myarray(4) <= x"0000";
> > myarray(5) <= x"0000";
> > myarray(6) <= x"0064";
> > myarray(7) <= x"0000";
> > myarray(8) <= x"0000";
> > myarray(9) <= x"000A";
> > myarray(10) <= x"0000";
> > myarray(11) <= x"0000";
> > myarray(12) <= x"003C";
> > myarray(13) <= x"0000";
> > myarray(14) <= x"0000";
> > myarray(15) <= x"0064";
> >
> > process( reset,clk)
> > variable romvar:natural range 0 to 15;
> >
> > begin
> > if reset = '1' then
> > dout_sig <= (others=>'0');
> > valid_sig <='0';
> > romvar :=0;
> >
> > elsif (clk'event and clk='1') then
> > if en='1' then
> > dout_sig <= myarray (romvar);
> > valid_sig<='1';
> > romvar :=romvar + 1;
> > else
> > dout_sig <= myarray (romvar);
> > valid_sig<='0';
> > end if;
> > end if;
> > end process;
> >
> > dout <= dout_sig;
> > valid <=valid_sig;
> > end rtl;
> > -------------------------------------------------------------------------
> > Warnings given by Modelsim:
> >
> > do inromtbw.ndo
> > # ** Warning: (vlib-34) Library already exists at "work".
> > ###### inrom_translate.vhd(443): );
> > # WARNING[1]: inrom_translate.vhd(443): No default binding for
> > component: "x_mux2". (No entity named "x_mux2" was found)
> > ###### inrom_translate.vhd(455): );
> > # WARNING[1]: inrom_translate.vhd(455): No default binding for
> > component: "x_ff". (No entity named "x_ff" was found)
> > ###### inrom_translate.vhd(468): );
> > # WARNING[1]: inrom_translate.vhd(468): No default binding for
> > component: "x_xor2". (No entity named "x_xor2" was found)
> > ###### inrom_translate.vhd(472): );
> > # WARNING[1]: inrom_translate.vhd(472): No default binding for
> > component: "x_zero". (No entity named "x_zero" was found)
> > ###### inrom_translate.vhd(476): );
> > # WARNING[1]: inrom_translate.vhd(476): No default binding for
> > component: "x_one". (No entity named "x_one" was found)
> > ###### inrom_translate.vhd(714): );
> > # WARNING[1]: inrom_translate.vhd(714): No default binding for
> > component: "x_lut2". (No entity named "x_lut2" was found)
> > ###### inrom_translate.vhd(2994): );
> > # WARNING[1]: inrom_translate.vhd(2994): No default binding for
> > component: "x_lut3". (No entity named "x_lut3" was found)
> > ###### inrom_translate.vhd(3128): );
> > # WARNING[1]: inrom_translate.vhd(3128): No default binding for
> > component: "x_lut4". (No entity named "x_lut4" was found)
> > ###### inrom_translate.vhd(3203): );
> > # WARNING[1]: inrom_translate.vhd(3203): No default binding for
> > component: "x_or2". (No entity named "x_or2" was found)
> > ###### inrom_translate.vhd(3341): );
> > # WARNING[1]: inrom_translate.vhd(3341): No default binding for
> > component: "x_tri". (No entity named "x_tri" was found)
> > ###### inrom_translate.vhd(3450): );
> > # WARNING[1]: inrom_translate.vhd(3450): No default binding for
> > component: "x_inv". (No entity named "x_inv" was found)
> > ###### inrom_translate.vhd(3533): port map (O => GSR);
> > # WARNING[1]: inrom_translate.vhd(3533): No default binding for
> > component: "x_roc". (No entity named "x_roc" was found)
> > ###### inrom_translate.vhd(3535): port map (O => GTS);
> > # WARNING[1]: inrom_translate.vhd(3535): No default binding for
> > component: "x_toc". (No entity named "x_toc" was found)
> > # vsim -lib work -t 1ps inromtbw
> > # Loading C:/Modeltech_5.7g/win32/../std.standard
> > # Loading C:/Modeltech_5.7g/win32/../ieee.std_logic_1164(body)
> > # Loading C:/Modeltech_5.7g/win32/../ieee.std_logic_arith(body)
> > # Loading C:/Modeltech_5.7g/win32/../std.textio(body)
> > # Loading C:/Modeltech_5.7g/win32/../ieee.std_logic_textio(body)
> > # Loading C:/Modeltech_5.7g/win32/../vital2000.vital_timing(body)
> > # Loading C:\Xilinx6\vhdl\mti_se\simprim.vcomponents
> > # Loading C:/Modeltech_5.7g/win32/../vital2000.vital_primitives(body)
> > # Loading C:\Xilinx6\vhdl\mti_se\simprim.vpackage(body)
> > # Loading work.inromtbw(testbench_arch)
> > # Loading work.inrom(structure)
> > # ** Warning: (vsim-3473) Component 'romvar_madd_n0000_inst_cy_5_0' is
> > not bound.
> > # Time: 0 ps Iteration: 0 Region: /inromtbw/uut File:
> > inrom_translate.vhd
> > # ** Warning: (vsim-3473) Component 'valid_sig_1' is not bound.
> > # Time: 0 ps Iteration: 0 Region: /inromtbw/uut File:
> > inrom_translate.vhd
> > # ** Warning: (vsim-3473) Component 'mmux_n0001_inst_mux_f5_130' is
> > not bound.
> >
> > I can not use a Core generated ROM for this design due to some
> > restrictions I have in my other codes..Sorry for a rather long mail
> > and thanks in advance for any help!!

Hi Vikram,

This is my second message...I figured out the error and thought I
would reply here just in case some one else encountered the same issue

"Component is not bound/unbound" warnings come (as you said) when
Modelsim cant find the simprimlibraries.I had the libraries compiled
as I said but I was pointing to the wrong ones.

I needed to point to the one under C:\Xilinx6\vhdl\mti_se\simprim
instead of C:\Modelsim5.7g\xilinx_libs\simprim..

As soon as I fixed this, I got results as expected...Thanks for the
guidance.Now I can proceed with my design!!

Best Regards,
Sridhar


Vikram Pasham <[email protected]> wrote in message news:<[email protected]>...
> Looks like Simprim libraries are missing which includes components like
> x_lut2, x_ff etc. Post Ngdbuild or post PAR back annotated simulation files
> have these libraries included. Unisim libraries are behavioral models while
> Simprim libraries are gate level models. Did you compile these libraries?
>
> This answer record will guide you on doing backannotated simulations.
> http://support.xilinx.com/xlnx/xil_a...PagePath=10177
>
> Regards
> Vikram
>
> Sridhar Hegde wrote:
>
> > Hi,
> >
> > I am designing a simple ROM in VHDL and following is the code for
> > it.Xilinx ISE 6.2i doesn't seem to have any issues synthesizing the
> > design to a Virtex 2 chip(xc2v4000) or translating/mapping/routing the
> > design(Implementation process).
> >
> > When I use the test bench created by HDL bencher to see the results,
> > in Modelsim, a behavioral simulation shows be proper results but a
> > post translate simulation or anything beyond that like a Post Map or a
> > Post place and route simulation show a U on all output pins and
> > Modelsim gives me a number of warnings about "Unbound components"
> > shown below..
> >
> > Im stuck at this design phase and would appreciate any help from the
> > VHDL gurus out there...Heres the code:-
> >
> > -----------------------------------------------------------------------
> >
> > library IEEE;
> > use IEEE.STD_LOGIC_1164.ALL;
> > use IEEE.STD_LOGIC_ARITH.ALL;
> > -- Uncomment the following lines to use the declarations that are
> > -- provided for instantiating Xilinx primitive components.
> > --library UNISIM;
> > --use UNISIM.VComponents.all;
> >
> > entity inrom is
> > Port ( en : in std_logic;
> > clk : in std_logic;
> > dout : out std_logic_vector( 15 downto 0);
> > valid : out std_logic; --valid data is present on output when 1
> > reset : in std_logic
> > );
> > end inrom;
> >
> > architecture rtl of inrom is
> >
> > type array_rom is array (15 downto 0) of std_logic_vector( 15 downto
> > 0);
> > signal myarray : array_rom;
> > signal valid_sig:std_logic;
> > signal dout_sig : std_logic_vector(15 downto 0);
> > signal clk2: std_logic;
> >
> > begin
> >
> > myarray(0) <= x"0000";
> > myarray(1) <= x"0000";
> > myarray(2) <= x"0000";
> > myarray(3) <= x"003C";
> > myarray(4) <= x"0000";
> > myarray(5) <= x"0000";
> > myarray(6) <= x"0064";
> > myarray(7) <= x"0000";
> > myarray(8) <= x"0000";
> > myarray(9) <= x"000A";
> > myarray(10) <= x"0000";
> > myarray(11) <= x"0000";
> > myarray(12) <= x"003C";
> > myarray(13) <= x"0000";
> > myarray(14) <= x"0000";
> > myarray(15) <= x"0064";
> >
> > process( reset,clk)
> > variable romvar:natural range 0 to 15;
> >
> > begin
> > if reset = '1' then
> > dout_sig <= (others=>'0');
> > valid_sig <='0';
> > romvar :=0;
> >
> > elsif (clk'event and clk='1') then
> > if en='1' then
> > dout_sig <= myarray (romvar);
> > valid_sig<='1';
> > romvar :=romvar + 1;
> > else
> > dout_sig <= myarray (romvar);
> > valid_sig<='0';
> > end if;
> > end if;
> > end process;
> >
> > dout <= dout_sig;
> > valid <=valid_sig;
> > end rtl;
> > -------------------------------------------------------------------------
> > Warnings given by Modelsim:
> >
> > do inromtbw.ndo
> > # ** Warning: (vlib-34) Library already exists at "work".
> > ###### inrom_translate.vhd(443): );
> > # WARNING[1]: inrom_translate.vhd(443): No default binding for
> > component: "x_mux2". (No entity named "x_mux2" was found)
> > ###### inrom_translate.vhd(455): );
> > # WARNING[1]: inrom_translate.vhd(455): No default binding for
> > component: "x_ff". (No entity named "x_ff" was found)
> > ###### inrom_translate.vhd(468): );
> > # WARNING[1]: inrom_translate.vhd(468): No default binding for
> > component: "x_xor2". (No entity named "x_xor2" was found)
> > ###### inrom_translate.vhd(472): );
> > # WARNING[1]: inrom_translate.vhd(472): No default binding for
> > component: "x_zero". (No entity named "x_zero" was found)
> > ###### inrom_translate.vhd(476): );
> > # WARNING[1]: inrom_translate.vhd(476): No default binding for
> > component: "x_one". (No entity named "x_one" was found)
> > ###### inrom_translate.vhd(714): );
> > # WARNING[1]: inrom_translate.vhd(714): No default binding for
> > component: "x_lut2". (No entity named "x_lut2" was found)
> > ###### inrom_translate.vhd(2994): );
> > # WARNING[1]: inrom_translate.vhd(2994): No default binding for
> > component: "x_lut3". (No entity named "x_lut3" was found)
> > ###### inrom_translate.vhd(3128): );
> > # WARNING[1]: inrom_translate.vhd(3128): No default binding for
> > component: "x_lut4". (No entity named "x_lut4" was found)
> > ###### inrom_translate.vhd(3203): );
> > # WARNING[1]: inrom_translate.vhd(3203): No default binding for
> > component: "x_or2". (No entity named "x_or2" was found)
> > ###### inrom_translate.vhd(3341): );
> > # WARNING[1]: inrom_translate.vhd(3341): No default binding for
> > component: "x_tri". (No entity named "x_tri" was found)
> > ###### inrom_translate.vhd(3450): );
> > # WARNING[1]: inrom_translate.vhd(3450): No default binding for
> > component: "x_inv". (No entity named "x_inv" was found)
> > ###### inrom_translate.vhd(3533): port map (O => GSR);
> > # WARNING[1]: inrom_translate.vhd(3533): No default binding for
> > component: "x_roc". (No entity named "x_roc" was found)
> > ###### inrom_translate.vhd(3535): port map (O => GTS);
> > # WARNING[1]: inrom_translate.vhd(3535): No default binding for
> > component: "x_toc". (No entity named "x_toc" was found)
> > # vsim -lib work -t 1ps inromtbw
> > # Loading C:/Modeltech_5.7g/win32/../std.standard
> > # Loading C:/Modeltech_5.7g/win32/../ieee.std_logic_1164(body)
> > # Loading C:/Modeltech_5.7g/win32/../ieee.std_logic_arith(body)
> > # Loading C:/Modeltech_5.7g/win32/../std.textio(body)
> > # Loading C:/Modeltech_5.7g/win32/../ieee.std_logic_textio(body)
> > # Loading C:/Modeltech_5.7g/win32/../vital2000.vital_timing(body)
> > # Loading C:\Xilinx6\vhdl\mti_se\simprim.vcomponents
> > # Loading C:/Modeltech_5.7g/win32/../vital2000.vital_primitives(body)
> > # Loading C:\Xilinx6\vhdl\mti_se\simprim.vpackage(body)
> > # Loading work.inromtbw(testbench_arch)
> > # Loading work.inrom(structure)
> > # ** Warning: (vsim-3473) Component 'romvar_madd_n0000_inst_cy_5_0' is
> > not bound.
> > # Time: 0 ps Iteration: 0 Region: /inromtbw/uut File:
> > inrom_translate.vhd
> > # ** Warning: (vsim-3473) Component 'valid_sig_1' is not bound.
> > # Time: 0 ps Iteration: 0 Region: /inromtbw/uut File:
> > inrom_translate.vhd
> > # ** Warning: (vsim-3473) Component 'mmux_n0001_inst_mux_f5_130' is
> > not bound.
> >
> > I can not use a Core generated ROM for this design due to some
> > restrictions I have in my other codes..Sorry for a rather long mail
> > and thanks in advance for any help!!