FPGA Central

Hello,

For a low power application I would like to stop the clock feed into a FPGA
when enter “sleep mode”. This is a common practice or can be dangerous? And
if is dangerous why? Maybe a silly question but I want to be sure about
that! I use Lattice XP parts.



Thanks,

Dan.

Ndf wrote:
> Hello,
>
> For a low power application I would like to stop the clock feed into a FPGA
> when enter "sleep mode". This is a common practice or can be dangerous? And
> if is dangerous why? Maybe a silly question but I want to be sure about
> that! I use Lattice XP parts.
>
>
>
> Thanks,
>
> Dan.

Some things to consider:

How do you exit "sleep mode"?

Does this require the clock you're stopping?

If so does the clock signal still exist in a portion of the design?

Were you considering using the FPGA to stop its own clock or
use an external component? It may not be easy to stop the clock
internally if you need to meet a certain phase relationship with
external parts. Normally gating off a global clock will require
adding some logic between the clock input pin and the global
buffer (this would not be the case for parts with dynamic clock
select resources, such as EC/ECP - I'm not sure if XP has these).
It may be possible to fix phase problems with a PLL, but again
if you stop the input to the PLL you'll need to reset it when you
start the clock again. DLL's have similar issues. Also if you use
either of these, you'll have problems if you need to come up
operational within a few clock cycles of exiting "sleep mode".

Good Luck,
Gabor

Ndf wrote:

> Hello,
>
> For a low power application I would like to stop the clock feed into
a FPGA
> when enter “sleep mode”. This is a common practice or can be
dangerous? And
> if is dangerous why? Maybe a silly question but I want to be sure about
> that! I use Lattice XP parts.


You can stop the clock, and also reduce Vcc in some cases.

However, Static Icc on these new FPGAs can be a real killer!

Look at some of the new Power control Busses / Chips appearing, that are
designed to ramp the Vcc, as the clock scales.
Natsemi LP5550 is one example.
-jg

Ndf wrote:
> Hello,
>
> For a low power application I would like to stop the clock feed into a FPGA
> when enter "sleep mode". This is a common practice or can be dangerous? And
> if is dangerous why? Maybe a silly question but I want to be sure about
> that! I use Lattice XP parts.
>
>
>
> Thanks,
>
> Dan.
Hi Dan -
this is actually a 2-parter -
LatticeXP devices have DCS blocks(Dynamic Clock Selection) as part
of the global clock networks, and can be used to deactivate selected
clocks, reducing current for that clock domain.
LatticeXP, and MachXO, both also offer 'Sleep Mode', in that these
devices have built-in Flash memory, for boot-up. The SleepMode pin
deactivates the core power supply, and maintains voltage in the I/O,
which allows for very low power ( less than 100ua) standby current.
When exiting 'sleep mode' the core supply is re-activated, and the
device then auto-boots from flash on chip.

The marketing term is "INSTANT ON" but us FAEs prefer "less than 1
millisecond".

So, yes, you can disable clocks to save some power, while the device
remains active, or you can enter 'sleep mode' and save most of the
power. Sleep Mode is available on the 'C' version of each device in
the family. The 'C' version has an onboard regulator, so you can run
the device with a single 3.3v supply. The core operates at 1.2v,
(derived from the on chip regulator in the 'C' devices), we require
3.3v for VccAUX(used for thresholding and some housekeeping circuitry),
and the appropriate VccIO voltages.

thanks for aking -

Michael Thomas
Lattice SFAE - NY/NJ

> Hi Dan -
> this is actually a 2-parter -
> LatticeXP devices have DCS blocks(Dynamic Clock Selection) as part
> of the global clock networks, and can be used to deactivate selected
> clocks, reducing current for that clock domain.
> LatticeXP, and MachXO, both also offer 'Sleep Mode', in that these
> devices have built-in Flash memory, for boot-up. The SleepMode pin
> deactivates the core power supply, and maintains voltage in the I/O,
> which allows for very low power ( less than 100ua) standby current.
> When exiting 'sleep mode' the core supply is re-activated, and the
> device then auto-boots from flash on chip.
>
> The marketing term is "INSTANT ON" but us FAEs prefer "less than 1
> millisecond".
>
> So, yes, you can disable clocks to save some power, while the device
> remains active, or you can enter 'sleep mode' and save most of the
> power. Sleep Mode is available on the 'C' version of each device in
> the family. The 'C' version has an onboard regulator, so you can run
> the device with a single 3.3v supply. The core operates at 1.2v,
> (derived from the on chip regulator in the 'C' devices), we require
> 3.3v for VccAUX(used for thresholding and some housekeeping circuitry),
> and the appropriate VccIO voltages.
>
> thanks for aking -
>
> Michael Thomas
> Lattice SFAE - NY/NJ
>

Thanks,

I'll explore these features.



Dan.