FPGA Central

I'm fairly new to this FPGA work, so my apologies if this is silly.

I'm using Xilinx's StateCad software to implement a simply FSM (~30
states) with the intention of using a Spartan3, XC3S200.

I have a number of 12-bit buses coming into the FSM. Three of these buses
are IO buses -- I want to read data off of the bus in some states, and
write to the bus in other states. Seems like a reasonable request, eh?

The problem: I've laid out the vectors in StateCad, reading and writing to
the VHDL variable names in various states. Additionally, I have set the
tristate bit on these buses in the appropriate states. When StateCad
generates the VHDL, it pronounces these vectors as OUTPUT vectors. Hrm, a
little strange.

I tried to get around this by having a separate set of buses that are
dedicated input buses. The PCB would then just short the input bus pins to
the output bus pins, and I'd jockey buses around so the output buses would
be high-impedance when appropriate. I know, I know, what a kludge, but I
need this done ASAP.

Well, to make a long story short, I can't map the FSM to the device I'm
using (and I basically have to use this particular device) -- I'm using to
many IOB. So, I need to get rid of 3 of those dedicated input buses, and
get some actual IO buses.

Is there any way to do this in StateCad? Am I missing something simple
here? I only have ~4 days experience with the Xilinx software, so bear
that in mind.

Useful details on my StateCad configuration:

Options: Full Vector Support, Retain Output Values Datatype: std_logic,
Bit: std_logic, Vector: std_logic_vector VHDL output
Language Vendor: IEEE 1076


Anyway, any advice would be appreciated. Thanks.

-Jack


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Jack W. Holloway [email protected]