FPGA Central

The FIFO(addr_cntrl_fifo_inst) has two completely irrelevant clocks,
say Clock A(trn_clk_c) and Clock B(DDR2_CLK0). The frequency of Clock
A is 250MHz(Period: 4ns), and Clock B is 266MHz(Period: 3.75ns). Now
the problem comes when performing STA. The Timing Analyzer reports
that:

Slack: -10.394ns (requirement - (data path - clock path skew +
uncertainty))
Source: addr_cntrl_fifo_inst/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM8_RAMC
(RAM)
Destination: addr_cntrl_fifo_inst/BU2/U0/grf.rf/mem/gdm.dm/dout_i_23
(FF)
Requirement: 0.250ns
Data Path Delay: 2.008ns (Levels of Logic = 0)
Clock Path Skew: -8.259ns (3.005 - 11.264)
Source Clock: trn_clk_c rising at 56.000ns
Destination Clock: DDR2_CLK0 rising at 56.250ns

For certain path crossing the different clock domains, the auto
constraints turned out to be 0.25ns (4ns – 3.75ns). This is impossible
to achieve.

What should I do to pass the STA?

vcar,

I suspect this cross-domain path is the "first-word fall-through"
path: when you write the first word in the -empty- FIFO, it
immediately becomes available on the read port. In such, this path is
real. (With two clocks running at 4ns and 3.75ns, the smallest
distance between two edges is indeed .250ns*in each direction)

However, as a designer, if you know that this will never be exercised,
you need to declare it as a false path. In your case, you probably
should declare false paths between the two clocks (two constraints to
cover each direction), which will cover all paths crossing from one
clock to the other.

- gael

On Jun 28, 3:21*am, vcar <hi...@163.com> wrote:
> The FIFO(addr_cntrl_fifo_inst) has two completely irrelevant clocks,
> say Clock A(trn_clk_c) and Clock B(DDR2_CLK0). The frequency of Clock
> A is 250MHz(Period: 4ns), and Clock B is 266MHz(Period: 3.75ns). Now
> the problem comes when performing STA. The Timing Analyzer reports
> that:
>
> Slack: *-10.394ns (requirement - (data path - clock path skew +
> uncertainty))
> * Source: addr_cntrl_fifo_inst/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM8_RAMC
> (RAM)
> * Destination: addr_cntrl_fifo_inst/BU2/U0/grf.rf/mem/gdm.dm/dout_i_23
> (FF)
> * Requirement: * * * * 0.250ns
> * Data Path Delay: * * *2.008ns (Levels of Logic = 0)
> * Clock Path Skew: * * *-8.259ns (3.005 - 11.264)
> * Source Clock: * * * *trn_clk_c rising at 56.000ns
> * Destination Clock: * *DDR2_CLK0 rising at 56.250ns
>
> For certain path crossing the different clock domains, the auto
> constraints turned out to be 0.25ns (4ns – 3.75ns). This is impossible
> to achieve.
>
> What should I do to pass the STA?
The timing delay between the rising edges of 250 and 266 MHz is not
limited to 250 ps. (You got that false impression from the rounding
off to 3.75 ns) In reality, there is no lower limit at all, down to
the fractional femtoseconds. That is what makes the control of Full
and Empty flags so challenging.
Peter Alfke, Xilinx

Peter,

I suspect the OP actually constrained his clocks in ns, rounding
266Mhz to 3.75ns. That would explain why the STA calculates a 250ps
distance (which is correct for 3.75ns and 4ns clocks).
If not, this would show a bug in STA since the distance (i.e.
"Requirement") between the clocks should then be 0 (after rounding).

The issue though lies in declaring these clocks as unrelated,
typically with false paths.

- gael

There is the details information about my design for your better
understanding.

The async FIFO is common FIFO, not the first-word fall-through FIFO.

The Clock A and Clock B are generated by one clock source but from
different PLL/DCM. So ISE will auto relate the two clocks as related
clocks. All the signals in my design crossing clock A and clock B are
passing through async FIFO like the one I listed
(addr_cntrl_fifo_inst).

Since there is async FIFO which will handle the async clock domain
problem, I think my design should have two unrelated clocks, not the
related clocks. And all I need to do is to add false path on the
crossing paths between clock A & clock B. Am I right?

On Jun 28, 10:34*pm, Peter Alfke <al...@sbcglobal.net> wrote:
> On Jun 28, 3:21*am, vcar <hi...@163.com> wrote:
>
> > The FIFO(addr_cntrl_fifo_inst) has two completely irrelevant clocks,
> > say Clock A(trn_clk_c) and Clock B(DDR2_CLK0). The frequency of Clock
> > A is 250MHz(Period: 4ns), and Clock B is 266MHz(Period: 3.75ns). Now
> > the problem comes when performing STA. The Timing Analyzer reports
> > that:
>
> > Slack: *-10.394ns (requirement - (data path - clock path skew +
> > uncertainty))
> > * Source: addr_cntrl_fifo_inst/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM8_RAMC
> > (RAM)
> > * Destination: addr_cntrl_fifo_inst/BU2/U0/grf.rf/mem/gdm.dm/dout_i_23
> > (FF)
> > * Requirement: * * * * 0.250ns
> > * Data Path Delay: * * *2.008ns (Levels of Logic = 0)
> > * Clock Path Skew: * * *-8.259ns (3.005 - 11.264)
> > * Source Clock: * * * *trn_clk_c rising at 56.000ns
> > * Destination Clock: * *DDR2_CLK0 rising at 56.250ns
>
> > For certain path crossing the different clock domains, the auto
> > constraints turned out to be 0.25ns (4ns – 3.75ns). This is impossible
> > to achieve.
>
> > What should I do to pass the STA?
>
> The timing delay between the rising edges of 250 and 266 MHz is not
> limited to 250 ps. (You got that false impression from the rounding
> off to 3.75 ns) In reality, there is no lower limit at all, down to
> the fractional femtoseconds. That is what makes the control of Full
> and Empty flags so challenging.
> Peter Alfke, Xilinx

Hi Peter,

challenging does not mean "undoable" for Xilinx I hope?
because in one large project, there is again a showstopper
and it is now because of xilinx coregen FIFO flags do not
seem to work properly

unfortunatly adding chipscope to the FPGA design makes
the MPMC2 DDR2 memory to fail so the system debug
is not possible. Simulation the full design is also not possible
the client does not have centuries to wait for simulation results.

is it OK, to expect that ISE 10.1 SP3 coregen FIFO's work?

or do they all work just under ideal case scenario and actually
fail in each and every real design?

those fifos and the debugging isnt my task in that project
i was just asked to help out with DEBUGGING the coregen
FIFO's but we have hard time with that

Antti

On Sun, 28 Jun 2009 19:48:33 -0700 (PDT), vcar <hitsx@163.com> wrote:

>Since there is async FIFO which will handle the async clock domain
>problem, I think my design should have two unrelated clocks, not the
>related clocks. And all I need to do is to add false path on the
>crossing paths between clock A & clock B. Am I right?

I think so.

If you tell the STA tool that the two clocks are unrelated
(different clock groups) then it should automatically cut
all paths between the two clock domains; there should be
no need to set false paths.

You DO need false paths if the two clocks really are
related, so that some paths need to be timed, but your
FIFO (or whatever) removes the need for STA on
certain paths between the two clock domains.

Which STA tool are you using?
--
Jonathan Bromley, Consultant

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I just used the ISE integrated tool called 'Timing Analyzer'.

So whether could I draw the conclusion that : "Async FIFO can handle
two unrelated async clocks." ?