FPGA Central

Hello,
Let me right again in this forum on the same topic. But know in
English. Whatever my English is very poor.
I am working for about 4 month's ego with an ML405 Xilinx Virtex 4
board and I wanted now to implement a Software Defined Radio (SDR).
I understand everything that relates to SDR (theory, operation,
Etc..) Very good. Likewise, I also understand VHDL and VERILOG.
Now I would like to know if someone is thus also employs
An SDR Board on the above (or others) to implement appropriate
Experience exchange.

In following a detailed overview of what I Made now:

First, I strive times only to receive an AM signal.

Hardware is on the board as much: DA converter (LM4550)
National and an external A / D converters (LTC2208) by Linear
Technology. I have prepared all software developed
(ADC.vhd, DAC.vhd, DDC.vhd ,...)I make already the simulation. Now, I
must try my signals: and with a
Function generator, I would like to generate a sine wave, and then the
sine wave through the FPGA with the process by the AD and DA
converters. I Am suppose to have the same signals again after the
DAC.


Example.
Sine (1Khz) ----> ADC -> FPGA ---> DAC ---> sinus (1Khz)
I can hear something (signal) at the output (by the DA converter) with
the
Headphones. However, I cannot measure it with the oscilloscope.
I had already tried without much success, and ask what the problem
Lie? Whether it down sampling, or rather in a
Clock functions?


Did someone get an idea or a tip for me?


I look forward to all suggestions and thank you in advance...


Chindji

Chindgi,

My translation of your original post was not off target, after all.

So here is my original answer:

It seems like you have the conversion of the analog sine wave to digital
(AD), and conversion back again (DA) working in both VHDL, and hardware,
yet you say you can not see anything on the oscilloscope? Just because
you hear something in the headphones may be cross-talk (just a
coincidence caused by a secondary path - parasitic coupling).

First, did you simulate the design? Does the simulation test bench work?

Second, are you able to input, and output static (unchanging) DC
voltages? This would be my first test, before I tried AC (sine waves).

If this is an issue with clocking (sampling), the DC will work, and then
the AC will have issues with frequency response (just guessing).

If the DC does not work, then I would use a logic analyzer (if it is
Xilinx, Chipscope(tm) is soft IP that may be part of your design, and
allows you to probe your digital signals inside the FPGA and see if they
are what you expect in the DC case).

http://www.xilinx.com/ise/optional_prod/cspro.htm

Have fun,

Austin

[email protected] <[email protected]> wrote:
> Sine (1Khz) ----> ADC -> FPGA ---> DAC ---> sinus (1Khz)
> I can hear something (signal) at the output (by the DA converter)
> with the
> Headphones. However, I cannot measure it with the oscilloscope.

Why?

If you don't have an oscilloscope, try the poor man logic analyzer:
http://www.sump.org/projects/analyzer/

or (in german)

http://de.sump.org/projects/analyzer/

It can also display "digital" waveforms.

regards,
Bart