On Oct 13, 10:36 pm, uraniumore...@gmail.com wrote:
> Thanks for the help. So, I can insure myself that the FPGA is counting
> as long as the FPGA is always driven by some input square wave and not
> floting to some external squivering ? How would I verify that it is
> actually counting (despite the fact that the count value got to the
> max) ? Any ideas ?
One thing you could do is counter periods of a faster clock between
the puleses to measure the inter-arrival time. Any substantial
irregularities probably indicate glitches (or an unstable source) You
would then need a way to dump that data out. You can do that manually
through the serial port but it takes a fair amount of coding. Does
the chipscope logic analyzer work on the webpack tools? If so that
would be a good way to monitor the data from this type of experiment
(you could also just clock the analyzer with a faster clock and look
at the input and expect to see a square wave, or have it look at your
count register)