FPGA Central

Hello all,
I am doing a design with block RAM. The register block is part of
the full design which is causing concern. The block diagram of the
register block is at the link
http://esnips.com/doc/58fb6919-cf9a-...ck_diagram.jpg
It consumes almost 8K of LUT and 3K of FFs and 128 BRAM in a V4Lx60.
And the total count is 33K of LUT.
The register block is operating in two clocks as shown in figure. clk1x
and clk4x = 4*clk1x.
The paths i want to be constrained are indicated with a * sign in the
block diagram. Initialy i was working with two independent clocks that
is clk1x and clk4x was comming externally. And i specified no relation
between these clocks. And was able to constrain the delay of the *
blocks upto 6ns. I gave only from to constrain. After the initial
experiments i included a DCM block to generate the clk1x and clk4x.
Which is also indicated in the diagram.
But now when i give period constrain to clk4x or clock in the
design is not routing. Why it is like that. I gave 10ns to clk4x
(initially it worked with 6ns) but stil is not routing. Applied area
group constrains to clk4x and clk1x domains the routing problem is
little bit reduced but still there. Now it shows initial time score as
3000000.
I want to understand what is the change happend to the design after
including a DCM to generate two clocks. Is there any special
consideration i should apply to the design.
One more thing i want to know is the routing delay between BRAM and
LUTs. As BRAM are spread in the entire chip. IS there any special
routing resource to handle this.
I am planning to include a buffer between the BRAM and the
combinational logic. And then clock the BRAM with -ve edge and latch
the values into buffer at +ve edge. Will that improve the timing.
PLease give your expert comments on these issues.
Thanks and regards
Sumesh V S

Also will there be any improvement in not specifying the global
constrain like setting period for the 4x clock and instead specifying
the needed constrain that is only the from to constarin for the blocks
i have indicated in the block diagram

Since you're using a DCM, you don't need to put a period constraint on
clk4x. You only need to specify the period on the clkin to the DCM and
the tool will automatically propagate this constraints to the DCM
outputs with correct phase adjustments. This of course requires you set
up the DCM attributes correctly.

You can run the timing analyzer to see why you got a very high timing
score and fix code and/or constraints accordingly.

HTH,
Jim
http://home.comcast.net/~jimwu88/tools/