FPGA Central

There was a thread about ring oscillators recently. I tried to build one in
a Xilinx V2Pro and found, as I suspected, that the ISE tools collapsed the
ring of inverters into a single inverter. I'm sure there is a simple way to
preserve the logic from being pruned by the tools by means of a constraint,
but I can't figure it out. What's the secret, short of routing each
inverter's output to an IOB to prevent pruning?

The frequency of the oscillator is not critical so I'm not worried about
placement or routing.
-Kevin

In article <6fO3d.84788$D%.79178@attbi_s51>,
Kevin Neilson <[email protected]> wrote:
>There was a thread about ring oscillators recently. I tried to build one in
>a Xilinx V2Pro and found, as I suspected, that the ISE tools collapsed the
>ring of inverters into a single inverter.

Maybe the KEEP attribute would work?

http://toolbox.xilinx.com/docsan/xil...gd0125_78.html

--
Ben Jackson
<[email protected]>
http://www.ben.com/

Ben,

KEEP or SAVE.

Austin

Ben Jackson wrote:

> In article <6fO3d.84788$D%.79178@attbi_s51>,
> Kevin Neilson <[email protected]> wrote:
>
>>There was a thread about ring oscillators recently. I tried to build one in
>>a Xilinx V2Pro and found, as I suspected, that the ISE tools collapsed the
>>ring of inverters into a single inverter.
>
>
> Maybe the KEEP attribute would work?
>
> http://toolbox.xilinx.com/docsan/xil...gd0125_78.html
>

Austin Lesea wrote:
> Ben,
>
> KEEP or SAVE.
>
> Austin
>
> Ben Jackson wrote:
>
>> In article <6fO3d.84788$D%.79178@attbi_s51>,
>> Kevin Neilson <[email protected]> wrote:
>>
>>> There was a thread about ring oscillators recently. I tried to build
>>> one in
>>> a Xilinx V2Pro and found, as I suspected, that the ISE tools
>>> collapsed the
>>> ring of inverters into a single inverter.
>>
>>
>>
>> Maybe the KEEP attribute would work?
>>
>> http://toolbox.xilinx.com/docsan/xil...gd0125_78.html
>>
>>
Thanks, guys. I used KEEP and SAVE and had to really fight the tools to
keep everything from getting pruned and merged, but I finally got it to
work.
-Kevin

Until you compile it on a different revision of the tools :-O

In circumstances like this, I find it easier to just instantiate the primitives for
what you want, taking away any room for 'creativity' by the tools. Instantiation
also lets you place the bits so that you can get reasonably consistent timing from
run to run.

Kevin Neilson wrote:

>
> >>
> Thanks, guys. I used KEEP and SAVE and had to really fight the tools to
> keep everything from getting pruned and merged, but I finally got it to
> work.
> -Kevin

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email [email protected]
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

I also found it helpful to constrain the routing to obtain consistent
timing. As Peter mentioned last time, you could also try using the carry
chain for delay, and that considerably reduces the variation due to
routing differences.

/Siva

On Wed, 22 Sep 2004, Ray Andraka wrote:

> Until you compile it on a different revision of the tools :-O
>
> In circumstances like this, I find it easier to just instantiate the primitives for
> what you want, taking away any room for 'creativity' by the tools. Instantiation
> also lets you place the bits so that you can get reasonably consistent timing from
> run to run.
>
> Kevin Neilson wrote:
>
> >
> > >>
> > Thanks, guys. I used KEEP and SAVE and had to really fight the tools to
> > keep everything from getting pruned and merged, but I finally got it to
> > work.
> > -Kevin
>