FPGA Central

Hi,
I am creating an FPGA (Spartan 3 XCS400) based replacement for one of our
old board designs which uses IDT 7201 -
http://www.idt.com/products/files/42...00-7202_DS.pdf.

Initially I cheated a little and created a clock for the FIFOs and lined up
my stimulus to that clock and worked out the bugs in my design.

To actually match the original board however I need to work without a
clock - the board I am replacing is controlled by another board with a
32MHz clock on it but that clock does not pass down the backplane to my
board so all I have are various signals that I must act on.

Most of the design seems to work fine except for a limitation in the FIFO
core (I am using the Xilinx async FIFO core v6.1) - it must get few clocks
from each domain after a reset otherwise it will not accept writes (or
reads presumably but it's hard to tell).

I did put a 50MHz clock on my board Just In Case(tm) however, obviously, it
won't be synchronised with the clock on the main card so I need to sync up
the incoming reset signal and then count out a few clocks to the FIFO core.

I'm still working on the last part trying to get it working but since my
design reads like a "How not to use an FPGA" (through no fault of my
own! plus I am normally a software guy, it's hard going.

Has anyone done this sort of thing before? (and would be willing to share
their solution).

I am also considering taking the 50MHz clock on my board and multiplying it
up to, say, 150MHz and sychronising/one-shotting all of the signals from
the other board to that.

--
Daniel O'Connor software and network engineer
for Genesis Software - http://www.gsoft.com.au
"The nice thing about standards is that there
are so many of them to choose from."
-- Andrew Tanenbaum
GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8C

Daniel O'Connor wrote:
> I am also considering taking the 50MHz clock on my board and multiplying it
> up to, say, 150MHz and sychronising/one-shotting all of the signals from
> the other board to that.

Yep. That's the what you have to do. All other routes lead to madness.
Synchronize the incoming signals and as much of the rest as possible. I
would look hard at making the FIFO synchronous.

On Feb 8, 3:41 am, Tim <s...@nooospam.roockyloogic.com> wrote:
> Daniel O'Connor wrote:
> > I am also considering taking the 50MHz clock on my board and multiplying it
> > up to, say, 150MHz and sychronising/one-shotting all of the signals from
> > the other board to that.
>
> Yep. That's the what you have to do. All other routes lead to madness.
> Synchronize the incoming signals and as much of the rest as possible. I
> would look hard at making the FIFO synchronous.

Since you have to synchronize to a new clock anyhow, make the whole
FIFO synchronous (same clock for write and read, but with separate
Enables). That makes the FIFO design very simple, and avoids all the
tricky circuitry requires for asynchronous operation.
Peter Alfke, Xilinx

Tim wrote:

> Daniel O'Connor wrote:
>> I am also considering taking the 50MHz clock on my board and multiplying
>> it up to, say, 150MHz and sychronising/one-shotting all of the signals
>> from the other board to that.
>
> Yep. That's the what you have to do. All other routes lead to madness.
> Synchronize the incoming signals and as much of the rest as possible. I
> would look hard at making the FIFO synchronous.

I guess that explains the pounding headaches then

--
Daniel O'Connor software and network engineer
for Genesis Software - http://www.gsoft.com.au
"The nice thing about standards is that there
are so many of them to choose from."
-- Andrew Tanenbaum
GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8C

Peter Alfke wrote:
>> Yep. That's the what you have to do. All other routes lead to madness.
>> Synchronize the incoming signals and as much of the rest as possible. I
>> would look hard at making the FIFO synchronous.
>
> Since you have to synchronize to a new clock anyhow, make the whole
> FIFO synchronous (same clock for write and read, but with separate
> Enables). That makes the FIFO design very simple, and avoids all the
> tricky circuitry requires for asynchronous operation.

OK, I am using the Xilinx core so the complexity of it's internal design
doesn't bother me much

I'll do as you suggest though as it makes sense to avoid the potential
testing pitfalls

Thanks for the input.

--
Daniel O'Connor software and network engineer
for Genesis Software - http://www.gsoft.com.au
"The nice thing about standards is that there
are so many of them to choose from."
-- Andrew Tanenbaum
GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8C

To quote Albert Einstein:
"Make everything as simple as possible, but not simpler".
Good advice!
Peter Alfke

On Feb 8, 10:03 pm, Daniel O'Connor <dar...@dons.net.au> wrote:
> Tim wrote:
> > Daniel O'Connor wrote:
> >> I am also considering taking the 50MHz clock on my board and multiplying
> >> it up to, say, 150MHz and sychronising/one-shotting all of the signals
> >> from the other board to that.
>
> > Yep. That's the what you have to do. All other routes lead to madness.
> > Synchronize the incoming signals and as much of the rest as possible. I
> > would look hard at making the FIFO synchronous.
>
> I guess that explains the pounding headaches then
>
> --
> Daniel O'Connor software and network engineer
> for Genesis Software -http://www.gsoft.com.au
> "The nice thing about standards is that there
> are so many of them to choose from."
> -- Andrew Tanenbaum
> GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8C