FPGA Central

Hi,

I am write and read from a text file using vhdl. I am using quartus
4.0 to compile and simulate. when I compile the code below, it said
that the writeline, write functions are not synthesis, which is
correct. Then when I simulate using simulator tools, it does not work,
and nothing get written to the "test_1.txt".

Did anyone try to do this in Quartus before? and what is the problems
in my code?

Thank you in advance for ur time and effort,
John.


Library IEEE;
use ieee.std_logic_1164.all;

use std.textio.all;

entity test_1_wrrd is

generic(
Input_File : string := "test_1.txt"
);

port ( a : in std_logic;
-- clk : in std_logic;
b : out std_logic;
s : in std_logic
);

end entity test_1_wrrd;

architecture beh of test_1_wrrd is

begin

Process(a, s)

file p_file : text open write_mode is Input_File ;
Variable l : Line;


Begin


if s = '1' then

b <= '1';


Write ( l, "a");
Writeline ( p_file, l );



else

b <= '0';

end if;



End Process;
End beh;

John wrote:

> Hi,
>
> I am write and read from a text file using vhdl. I am using quartus
> 4.0 to compile and simulate. when I compile the code below, it said
> that the writeline, write functions are not synthesis, which is
> correct. Then when I simulate using simulator tools, it does not work,
> and nothing get written to the "test_1.txt".
>
> Did anyone try to do this in Quartus before? and what is the problems
> in my code?

Quartus has absolutely nothing to do with this. Do not try to synthesize
a test bench, since it would mean you want your FPGA to write into a file ;-)
You must use a VHDL simulator like ModelSim (AE or other) for this to work.

To make it simple : Quartus is for synthesis, ModelSim is for simulation.

Otherwise, the code has the principle of text io, so it should _almost_ work.
I'm suspicious here because you didn't say the simulator rejected your
code, which it should have, since "a" is ambiguous !
I suspect you didn't simulate, opr compile, or instanciate test_1_wrrd,
or s is not '1' while a changes, etc... etc....

In case of doubt, load your test bench, make sure you can get into
the test_1_wrrd instance, and place a breakpoint.

Oh, about ambiguity : try Ht & "a" instead :-)

And if you wanted to record the value of the a input,
then you should have written write (l,a); .... but that wouldn't
have worked either since you missed :
use ieee.std_logic_textio.all;

Keep faith...

Bert Cuzeau


>
> Thank you in advance for ur time and effort,
> John.
>
>
> Library IEEE;
> use ieee.std_logic_1164.all;
>
> use std.textio.all;
>
> entity test_1_wrrd is
>
> generic(
> Input_File : string := "test_1.txt"
> );
>
> port ( a : in std_logic;
> -- clk : in std_logic;
> b : out std_logic;
> s : in std_logic
> );
>
> end entity test_1_wrrd;
>
> architecture beh of test_1_wrrd is
>
> begin
>
> Process(a, s)
>
> file p_file : text open write_mode is Input_File ;
> Variable l : Line;
>
>
> Begin
>
>
> if s = '1' then
>
> b <= '1';
>
>
> Write ( l, "a");
> Writeline ( p_file, l );
>
>
>
> else
>
> b <= '0';
>
> end if;
>
>
>
> End Process;
> End beh;