FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 08-06-2003, 02:17 PM
Paul Burke
Guest
 
Posts: n/a
Default Re: Questions in Altera FPGA MegaCore Compact-PCI Configuration Spaceunder Windows NT

Beeson Wong wrote:

> Hi,
>
> When the host is a 'MEN F0001 Power-PC'
> card, I used the provided MENMOM on-board
> utility ('PCID') to dump out the PCI
> configuration spaces of both cards (PLX9030
> and Altera MegaCore). Both gave me expected
> results.
>
> When the host is a 'PEP CP302 Intel'. I
> used two publicly available utilities: WinDriver
> under Windows NT and PLXMon under DOS. Both
> utilities did not dump out the expected
> configuration space values for Altera/MegaCore
> card (e.g. the Vendor ID and Device ID were
> OK, but all the BARs were zeros). However, the
> configuration space for PLX9030 was OK.
>
> It seems the operating systems (Windows NT
> and/or DOS) on the host did not allocate resources
> for the Altera/FPGA card.
>
>



I have had problems with the PLX PCI9052 and certain versions of the
Compaq EVO series. It appears to be a BIOS problem, they aren't allowing
the PLX chip enough time to load from the EEPROM. At least, that was
PLX's view of the problem (of course, Compaq never replied so I don't
know what theirs is).

If your end system is DOS based, if you poke the correct values to the
registers, it works fine thereafter. I expect you can do it with some
Windows versions too, though not NT, MX etc. But plug and play might
mess things up if any hot plugging happens.

Paul Burke

Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
comp.unix.cray,comp.windows.garnet,comp.os.ms-windows.programmer.winhelp,comp.os.ms-windows.networking.tcp-ip,comp.lang.verilog . Verilog 0 06-19-2004 10:15 AM


All times are GMT +1. The time now is 03:25 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2012, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved