FPGA Central

#1 (**permalink**) 08-04-2003, 09:27 PM

Pankaj Rodey wrote:

> I have a querry regarding CPLD, we are using. It is XC9536XL and
> XC9572TQ100 Xilinx CPLDs.
> I tried to develop a simple divide by two scheme, with a T flip flop,
> with T pin tied high and clock given to flip flop through one of the
> global clock I/O pins of CPLD. It is expected to get pulses of half
> the frequency at Q output of the flip flop, with Q output toggling at
> every positive edge of clock. However, I get some pulses of
> continually varying frequency at the output pin.
> The devices I used are, XILINX WEBPACK ISE 4.2 as HDL editor, Impact
> tool for program download.
> Kindly guide me as to the possible sources this ambiguity.

Why not try a D flip-flop with the not-Q output connected back to the D
input.

Jon

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