FPGA Central

Jeff Cunningham wrote:
> Is it still true that BRAM arrays with different width ports cannot be
> inferred?
>
> Also, are the BRAM parity bits usable with inference, i.e. can you infer
> a 36 bit wide memory into a single BRAM?
>
> Coregen left a bad taste in my mouth last time I tried to use it for
> BRAM. Instead I find directly instantiating BRAM instances with use of
> the VHDL generate statement to be fairly powerful and flexible.
>
> -Jeff

I believe so. I made my own dual port ram component that looks at the
data and address port widths on both ports to figure out the
construction of the composite memory. It is limited in depth to the
BRAM depths (up to 16K), as it doesn't use any multiplexers. It also
accepts initial ram values as an array of integers and takes care of
splitting those up among parallelled BRAMs as needed. It took a while
to develop and test the component, but since I do as many designs as I
do, it has more than paid for itself in time saved on subsequent designs.