FPGA Central

Anything is possible,

But you can't use 90nm for 5V. The minimum size you can use is .35u.

A combo 90 nm/ .35u process is not in the roadmap, so that makes life a bit
tough.

But then again, where is the $?

Peter and I are engineers, not marketeers, so we defer to the marketing folks
who seem to know just how large (small) the 5V market is....

Austin

"B. Joshua Rosen" wrote:

> Peter, Austin,
>
> Is it possible to build 5V IOs on a 90nm process? The world is full of
> antique buses that aren't going to go away anytime soon. A couple of
> medium sized devices targeted at the legacy bus interface market would be
> useful. I'd suggest doing two devices, a XC3S1500 and a XC3S400 with
> 5V/3.3V IOs. You could toss the multipliers, those aren't useful in this
> application, as well as all of the fancy modern IO standards which also
> aren't needed for this application, block RAM is important because bridges
> need large FIFOs. The other thing that you would want to do is modify the
> DCM so that it could support lower clock frequencies, 10Mhz -20Mhz is
> common in this world.

Austin Lesea wrote:
>
> Anything is possible,
>
> But you can't use 90nm for 5V. The minimum size you can use is .35u.
>
> A combo 90 nm/ .35u process is not in the roadmap, so that makes life a bit
> tough.
>
> But then again, where is the $?
>
> Peter and I are engineers, not marketeers, so we defer to the marketing folks
> who seem to know just how large (small) the 5V market is....
>
> Austin

At what process size does the 3.3 volt compatibility go away?

I have never understood why the voltage is a problem. I understand that
the thin oxide for the gate will not take the voltage. But I don't see
why the IO transistors can't be made with thicker oxides. All chips
have thick oxides all over the chip on many layers for isolation. Seems
pretty simple to add one more oxide layer for the IO transistor gates.

I understand that this will slow the chip IO a bit and may add a bit of
cost, but it is no technical hurdle and 5 volt is still a market. To be
able to address the 5 volt sockets in addition to the regular market
seems to be a win-win.

--

Rick "rickman" Collins

[email protected]
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

Austin Lesea <[email protected]> wrote:
....

: If you havce 90nm/.35u (no reason why it can't be done), you lose all your
: speed and area by having to drive the huge .35u transistors (makes for a
: more expensive die).

Austin,

just for interest, is there any document showing the schematics of such a
mixed voltage output stage? I think driving the PMOS of the output stage is
quite tricky, without sacrificing to much current.

Bye
--
Uwe Bonnes [email protected]

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

On Mon, 04 Aug 2003 09:46:48 -0700, Austin Lesea wrote:

> Rick,
>
> It has to do with the foundires.
>
> What do you offer as your lowest cost standard CMOS process?
>
> .18/.35 was really popular (and still is).
>
> .15/.35 was the half-step between .18 and .13.
>
> .13/.25 is the dominat process right now (3.3V is a tough push, and has to
> be done carefully, and 5V is definitely gone)
>
> 90nm/.25u is what we are in for Spartan 3, so there has to be a reason
> (like all those three letter companies that offer standard CMOS
> processes....)
>
> If you havce 90nm/.35u (no reason why it can't be done), you lose all your
> speed and area by having to drive the huge .35u transistors (makes for a
> more expensive die).

Are you saying that you lose all of the speed and area over the whole die
or just for the IO section? If it's just the IO that would be OK in a part
like this. A part aimed at the 5V interface market doesn't need fast IOs
because the clock rates in that world are low. It does need the logic and
RAM density of a modern part, if it wasn't any denser than an old .18u
part then you might as well stick with the older part or live with
external level shifting transceivers.

Uwe,

Circuits to do this are considered proprietary.

I could do a search on google for level shifters, but you can, too.

Austin

Uwe Bonnes wrote:

> Austin Lesea <[email protected]> wrote:
> ...
>
> : If you havce 90nm/.35u (no reason why it can't be done), you lose all your
> : speed and area by having to drive the huge .35u transistors (makes for a
> : more expensive die).
>
> Austin,
>
> just for interest, is there any document showing the schematics of such a
> mixed voltage output stage? I think driving the PMOS of the output stage is
> quite tricky, without sacrificing to much current.
>
> Bye
> --
> Uwe Bonnes [email protected]
>
> Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

This is left as an exercise for those who already know how to design these
circuits,

If you don't, then it is not my place to instruct.

Austin

"B. Joshua Rosen" wrote:

> On Mon, 04 Aug 2003 09:46:48 -0700, Austin Lesea wrote:
>
> > Rick,
> >
> > It has to do with the foundires.
> >
> > What do you offer as your lowest cost standard CMOS process?
> >
> > .18/.35 was really popular (and still is).
> >
> > .15/.35 was the half-step between .18 and .13.
> >
> > .13/.25 is the dominat process right now (3.3V is a tough push, and has to
> > be done carefully, and 5V is definitely gone)
> >
> > 90nm/.25u is what we are in for Spartan 3, so there has to be a reason
> > (like all those three letter companies that offer standard CMOS
> > processes....)
> >
> > If you havce 90nm/.35u (no reason why it can't be done), you lose all your
> > speed and area by having to drive the huge .35u transistors (makes for a
> > more expensive die).
>
> Are you saying that you lose all of the speed and area over the whole die
> or just for the IO section? If it's just the IO that would be OK in a part
> like this. A part aimed at the 5V interface market doesn't need fast IOs
> because the clock rates in that world are low. It does need the logic and
> RAM density of a modern part, if it wasn't any denser than an old .18u
> part then you might as well stick with the older part or live with
> external level shifting transceivers.

Austin Lesea <[email protected]> wrote:
: Uwe,

: Circuits to do this are considered proprietary.

: I could do a search on google for level shifters, but you can, too.

The basic concept is clear for me. An Open Collector/OpenDrain as switch and
a pullup resistor ( in the discret case) or a depletion NMOS( in the
integrated case) as load. But to get that at speed at low current ...

Bye

--
Uwe Bonnes [email protected]

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------