FPGA Central

I have a device that require a free running clock with 0.5V DC offset
and 500mv swing. (0.25V VIL and 0.75V VIH). I am using Spartan3
1000 FPGA and all the outputs are connected to 3.3V bank.

Your ideas are most welcome.

Thanks.

CP

On Mon, 22 Jun 2009 09:21:22 -0700 (PDT), Test01 <cpandya@yahoo.com>
wrote:

>I have a device that require a free running clock with 0.5V DC offset
>and 500mv swing. (0.25V VIL and 0.75V VIH). I am using Spartan3
>1000 FPGA and all the outputs are connected to 3.3V bank.

Is this differential or single-ended? And what frequency?
---
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com

On Jun 22, 11:52*am, Muzaffer Kal <k...@dspia.com> wrote:
This is a single ended signal running at 32KHz. It is a free running
clock running at 32KHz.

> On Mon, 22 Jun 2009 09:21:22 -0700 (PDT), Test01 <cpan...@yahoo.com>
> wrote:
>
> >I have a device that require a free running clock with 0.5V DC offset
> >and 500mv swing. *(0.25V VIL and 0.75V VIH). * I am using Spartan3
> >1000 FPGA and all the outputs are connected to 3.3V bank.
>
> Is this differential or single-ended? And what frequency?
> ---
> Muzaffer Kal
>
> DSPIA INC.
> ASIC/FPGA Design Serviceshttp://www.dspia.com

On Mon, 22 Jun 2009 10:46:51 -0700 (PDT), Test01 wrote:

>This is a single ended signal running at 32KHz. It is a free running
>clock running at 32KHz.

In which case I suggest you think about a few resistors
and some simple circuit calculations :-)
--
Jonathan Bromley, Consultant

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jonathan.bromley@MYCOMPANY.com
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The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

On Mon, 22 Jun 2009 10:46:51 -0700 (PDT), Test01 <cpandya@yahoo.com>
wrote:

>On Jun 22, 11:52*am, Muzaffer Kal <k...@dspia.com> wrote:
>This is a single ended signal running at 32KHz. It is a free running
>clock running at 32KHz.
>
>> On Mon, 22 Jun 2009 09:21:22 -0700 (PDT), Test01 <cpan...@yahoo.com>
>> wrote:
>>
>> >I have a device that require a free running clock with 0.5V DC offset
>> >and 500mv swing. *(0.25V VIL and 0.75V VIH). * I am using Spartan3
>> >1000 FPGA and all the outputs are connected to 3.3V bank.

You should be able to make it work with a %1 500+100 ohm voltage
divider at the output of your 3.3V IO which puts your VOHmin around
0.5V. If your clock input capacitance is too high and you get slew
rate issues, you can add a transistor driver.
-
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

Hi MUzaffer,

You mentioned about using 500/100 Oho voltage divider. I am trying to
understand the amplitude.

For 3.3V output signal at 32KHz, when the output is at 3.3V, the
voltage divider will generate 0.55V

When the fpga Output pin is at 0V, the voltage divider will generate
0V.

Thus it will swing from 0 to 0.55V. Is that correct? I have Vih
requirement of 0.75 and Vil requirement of 0.25. I am not sure this
is considered meeting that requirement.

Thanks.

CP

On Jun 22, 2:03*pm, Muzaffer Kal <k...@dspia.com> wrote:
> On Mon, 22 Jun 2009 10:46:51 -0700 (PDT), Test01 <cpan...@yahoo.com>
> wrote:
>
> >On Jun 22, 11:52*am, Muzaffer Kal <k...@dspia.com> wrote:
> >This is a single ended signal running at 32KHz. *It is a free running
> >clock running at 32KHz.
>
> >> On Mon, 22 Jun 2009 09:21:22 -0700 (PDT), Test01 <cpan...@yahoo.com>
> >> wrote:
>
> >> >I have a device that require a free running clock with 0.5V DC offset
> >> >and 500mv swing. *(0.25V VIL and 0.75V VIH). * I am using Spartan3
> >> >1000 FPGA and all the outputs are connected to 3.3V bank.
>
> You should be able to make it work with a %1 500+100 ohm voltage
> divider at the output of your 3.3V IO which puts your VOHmin around
> 0.5V. If your clock input capacitance is too high and you get slew
> rate issues, you can add a transistor driver.
> -
> Muzaffer Kal
>
> DSPIA INC.
> ASIC/FPGA Design Services
>
> http://www.dspia.com

On Jun 22, 2:17*pm, Test01 <cpan...@yahoo.com> wrote:
> Hi MUzaffer,
>
> You mentioned about using 500/100 Oho voltage divider. *I am trying to
> understand the amplitude.
>
> For 3.3V output signal at 32KHz, when the output is at 3.3V, the
> voltage divider will generate 0.55V
>
> When the fpga Output pin is at 0V, the voltage divider will generate
> 0V.
>
> Thus it will swing from 0 to 0.55V. *Is that correct? *I have Vih
> requirement of 0.75 and Vil requirement of 0.25. *I am not sure this
> is considered meeting that requirement.
>
> Thanks.
>
> CP
>
> On Jun 22, 2:03*pm, Muzaffer Kal <k...@dspia.com> wrote:
>
>
>
> > On Mon, 22 Jun 2009 10:46:51 -0700 (PDT), Test01 <cpan...@yahoo.com>
> > wrote:
>
> > >On Jun 22, 11:52*am, Muzaffer Kal <k...@dspia.com> wrote:
> > >This is a single ended signal running at 32KHz. *It is a free running
> > >clock running at 32KHz.
>
> > >> On Mon, 22 Jun 2009 09:21:22 -0700 (PDT), Test01 <cpan...@yahoo.com>
> > >> wrote:
>
> > >> >I have a device that require a free running clock with 0.5V DC offset
> > >> >and 500mv swing. *(0.25V VIL and 0.75V VIH). * I am using Spartan3
> > >> >1000 FPGA and all the outputs are connected to 3.3V bank.
Also with simple voltage divider my DC offset will be around 0.25V and
not 0.5V. Thus it may not work having a voltage divider. is that
correct?

> > You should be able to make it work with a %1 500+100 ohm voltage
> > divider at the output of your 3.3V IO which puts your VOHmin around
> > 0.5V. If your clock input capacitance is too high and you get slew
> > rate issues, you can add a transistor driver.
> > -
> > Muzaffer Kal
>
> > DSPIA INC.
> > ASIC/FPGA Design Services
>
> >http://www.dspia.com- Hide quoted text -
>
> - Show quoted text -

Test01 <cpandya@yahoo.com> wrote:

> Also with simple voltage divider my DC offset will be around 0.25V and
> not 0.5V. Thus it may not work having a voltage divider. is that
> correct?

You need a not-so-simple voltage divider, with a resistor
to ground, Vcc, and the output.

-- glen