FPGA Central

Hi,

I have read several appnotes about serial interfaces in Xilinx FPGAs.
Most of them use a DCM on the receiving side to phase shift and/or
multiply the incoming clock. My problem is that I don't have any
global clock pins available, only clock capable. So when I use a DCM,
XST gives me an error that I am using a non-optimal IOB site for clock
input. The error can be reduced to a warning be setting a constraint
that allows the non-optimal clock input.

What are the implications of using the non-optimal IOB for clock
input?
Would it be better to try to find a solution that does not include a
DCM in the receiver?

Hello,

If you do not use a global clock input, then the worst case skews and
delays are no longer guaranteed.

If you use the phase shift in the DCM to find the center of the "eye" in
order to sample the received data, this means a single fixed phase shift
value may not work for all silicon.

If you use the variable "find the center" design which sets the phase
shift for each device after a training interval, then this will always
find the best sampling point, and the added skew or delay of using a
non-global input will not matter.

Austin