FPGA Central

Dear All,

I am encountering some troubles with quartus fitter, the fitter auto
assign a pin on an already assign pin here is the report of the
fitter :

Info: Fitter is performing an Auto Fit compilation, which may decrease
Fitter effort to reduce compilation time
Warning: Feature LogicLock is not available with your current license
Info: Device migration not selected. If you intend to use device
migration later, you may need to change the pin assignments as they
may be incompatible with other devices
Info: Fitter converted 3 user pins into dedicated programming pins
Info: Pin ~ASDO~ is reserved at location G7
Info: Pin ~nCSO~ is reserved at location K9
Info: Pin ~LVDS195p/nCEO~ is reserved at location AD25
Error: Can't place multiple pins assigned to pin location Pin_AD25
(IOC_X95_Y2_N1)
Info: Pin iSW[7] is assigned to pin location Pin_AD25
(IOC_X95_Y2_N1)
Info: Pin ~LVDS195p/nCEO~ is assigned to pin location Pin_AD25
(IOC_X95_Y2_N1)

So I don't already understand where the pin LVDS195p/nCEO come from
and even more why the fitter put it on an assigned pin

(I am working on a Terasic board and I put the pin as it was given
with exemple)

Thx for your help