FPGA Central

hi
im using digilab XCR development board which has Xilinx XCR3064
CPLD.
I/O pins in this CPLD are said to be tristate.
but when im trying to use them as tristate
its not working as one?
i mean i want one of the I/O pin to go high impedance but its not?
can any one tell me how can i make I/O pin in CPLD high impedance?

Post the code that drives the outputs...
And what does the synthesiser say?
B

<[email protected]> wrote in message
news:1142270059.172147.157840@z34g[email protected] oups.com...
> hi
> im using digilab XCR development board which has Xilinx XCR3064
> CPLD.
> I/O pins in this CPLD are said to be tristate.
> but when im trying to use them as tristate
> its not working as one?
> i mean i want one of the I/O pin to go high impedance but its not?
> can any one tell me how can i make I/O pin in CPLD high impedance?
>

[email protected] wrote:
> hi
> im using digilab XCR development board which has Xilinx XCR3064
> CPLD.
> I/O pins in this CPLD are said to be tristate.
> but when im trying to use them as tristate
> its not working as one?
> i mean i want one of the I/O pin to go high impedance but its not?
> can any one tell me how can i make I/O pin in CPLD high impedance?

Using VHDL:

io_pin <= some_data when output_enable = '1' else 'Z';

If your output is a bus rather than a single pin:

io_bus <= some_data_bus when output_enable = '1' else (others => 'Z');

'Z' means that the pin(s) are set to high impedance.

HTH

-Dave Pollum

thers no problem with synthesizer nor simulation results
infact simulation results show the output in high impedance
but when i check(using logic probe) that on hardware its not in high
impedance

code is simple
2 inputs ( switches)
1 output (I/O pin)

dout <= din when cnt = '1' else 'Z';




Benjamin Todd wrote:
> Post the code that drives the outputs...
> And what does the synthesiser say?
> B
>
> <[email protected]> wrote in message
> news:[email protected] oups.com...
> > hi
> > im using digilab XCR development board which has Xilinx XCR3064
> > CPLD.
> > I/O pins in this CPLD are said to be tristate.
> > but when im trying to use them as tristate
> > its not working as one?
> > i mean i want one of the I/O pin to go high impedance but its not?
> > can any one tell me how can i make I/O pin in CPLD high impedance?
> >

[email protected] wrote:
> thers no problem with synthesizer nor simulation results
> infact simulation results show the output in high impedance
> but when i check(using logic probe) that on hardware its not in high
> impedance

Ummmm, how is the logic probe supposed to know that the pin is
tristated?

-a

<[email protected]> schrieb im Newsbeitrag
news:[email protected] oups.com...
> hi
> im using digilab XCR development board which has Xilinx XCR3064
> CPLD.
> I/O pins in this CPLD are said to be tristate.
> but when im trying to use them as tristate
> its not working as one?
> i mean i want one of the I/O pin to go high impedance but its not?
> can any one tell me how can i make I/O pin in CPLD high impedance?
>

Fitter standard I/O termination is bus keeper. You can select pullup or
float.

If you float the pins (in the implementaion-fitter properties), you must
insure, that no input pin is unconnected and floating.


MIKE

--
www.oho-elektronik.de
OHO-Elektronik
Michael Randelzhofer
FPGA und CPLD Mini Module
Klein aber oho !