FPGA Central

Hi all,
to be more clear about my problem with timing simulation
after i implement it using xilinx it is creating one TIME_SIM.VHD and
TIME_SIM.SDF file under the folder "timing"
it has an identifier "X_INV_PP" in both files when i compile
TIME_SIM.VHD it is giving an error
"Unknown identifier "X_INV_PP""
Cannot find component declaration
did anyone come across similar kind of problem.please help me out

thanks,


Regards
Ramakrishna

you need to compile the simmprim vhdl library first.
in your $XILINX directory under /vhdl/src/simprims
(replace $XILINX with your actual xilinx installation dir)

Aurash

[email protected] wrote:
> Hi all,
> to be more clear about my problem with timing simulation
> after i implement it using xilinx it is creating one TIME_SIM.VHD and
> TIME_SIM.SDF file under the folder "timing"
> it has an identifier "X_INV_PP" in both files when i compile
> TIME_SIM.VHD it is giving an error
> "Unknown identifier "X_INV_PP""
> Cannot find component declaration
> did anyone come across similar kind of problem.please help me out
>
> thanks,
>
>
> Regards
> Ramakrishna
>