FPGA Central

Hi,

I am trying to place and route my design to a specific portion of the
FPGA
by using the Xilinx modular design flow, coupled with AREA_GROUP
constraints.
But the par for a module gives the following error message for some
(not all) region constraints.

FATAL_ERROR:Route:basrtareacst.c:891:1.18.2.1 - Failed to compute
route area
extrema. Process will terminate. To resolve this error, please
consult the
Answers Database and other online resources at
http://support.xilinx.com. If
you need further assistance, please open a Webcase by clicking on
the
"WebCase" link at http://support.xilinx.com

I am using Xilinx xc2v40 device and ISE 6.1. THe UCF file is:

INST "u1" AREA_GROUP=g1;
AREA_GROUP "g1" RANGE=SLICE_X0Y0:SLICE_X9Y5,SLICE_X10Y0:SLICE_X15Y 3;
AREA_GROUP g1 MODE=RECONFIG;
AREA_GROUP g1 PLACE=CLOSED;


Could not find any help in the answers database at Xilinx.
Can someone please help me?

Thanks in anticipation.
Aman

I did not mention this in the previous post. This error seems to be
coming only if I try to contrain the routing to non-rectangular
regions.
E.g.:
Following UCF works fine:
INST "u1" AREA_GROUP=g1;
AREA_GROUP "g1" RANGE=SLICE_X0Y0:SLICE_X11Y7;
AREA_GROUP g1 MODE=RECONFIG;
AREA_GROUP g1 PLACE=CLOSED;


But following does not:
INST "u1" AREA_GROUP=g1;
AREA_GROUP "g1" RANGE=SLICE_X0Y0:SLICE_X9Y5,SLICE_X10Y0:SLICE_X15Y 3;
AREA_GROUP g1 MODE=RECONFIG;
AREA_GROUP g1 PLACE=CLOSED;

Does this mean that I cannot constrain the routing to a region
composed of multiple rectangles like above? Or am I making some
mistake in the UCF?

I appreciate your reading this post.
Thanks,
Aman

[email protected] (Aman Gayasen) wrote in message news:<[email protected] om>...
> Hi,
>
> I am trying to place and route my design to a specific portion of the
> FPGA
> by using the Xilinx modular design flow, coupled with AREA_GROUP
> constraints.
> But the par for a module gives the following error message for some
> (not all) region constraints.
>
> FATAL_ERROR:Route:basrtareacst.c:891:1.18.2.1 - Failed to compute
> route area
> extrema. Process will terminate. To resolve this error, please
> consult the
> Answers Database and other online resources at
> http://support.xilinx.com. If
> you need further assistance, please open a Webcase by clicking on
> the
> "WebCase" link at http://support.xilinx.com
>
> I am using Xilinx xc2v40 device and ISE 6.1. THe UCF file is:
>
> INST "u1" AREA_GROUP=g1;
> AREA_GROUP "g1" RANGE=SLICE_X0Y0:SLICE_X9Y5,SLICE_X10Y0:SLICE_X15Y 3;
> AREA_GROUP g1 MODE=RECONFIG;
> AREA_GROUP g1 PLACE=CLOSED;
>
>
> Could not find any help in the answers database at Xilinx.
> Can someone please help me?
>
> Thanks in anticipation.
> Aman

On Mon, 11 Oct 2004 12:25:55 -0700, Aman Gayasen wrote:

> I did not mention this in the previous post. This error seems to be
> coming only if I try to contrain the routing to non-rectangular
> regions.
> E.g.:
> Following UCF works fine:
> INST "u1" AREA_GROUP=g1;
> AREA_GROUP "g1" RANGE=SLICE_X0Y0:SLICE_X11Y7;
> AREA_GROUP g1 MODE=RECONFIG;
> AREA_GROUP g1 PLACE=CLOSED;
>
>
> But following does not:
> INST "u1" AREA_GROUP=g1;
> AREA_GROUP "g1" RANGE=SLICE_X0Y0:SLICE_X9Y5,SLICE_X10Y0:SLICE_X15Y 3;
> AREA_GROUP g1 MODE=RECONFIG;
> AREA_GROUP g1 PLACE=CLOSED;
>
> Does this mean that I cannot constrain the routing to a region
> composed of multiple rectangles like above? Or am I making some
> mistake in the UCF?
>
> I appreciate your reading this post.
> Thanks,
> Aman
>
> [email protected] (Aman Gayasen) wrote in message news:<[email protected] om>...
>> Hi,
>>
>> I am trying to place and route my design to a specific portion of the
>> FPGA
>> by using the Xilinx modular design flow, coupled with AREA_GROUP
>> constraints.
>> But the par for a module gives the following error message for some
>> (not all) region constraints.
>>
>> FATAL_ERROR:Route:basrtareacst.c:891:1.18.2.1 - Failed to compute
>> route area
>> extrema. Process will terminate. To resolve this error, please
>> consult the
>> Answers Database and other online resources at
>> http://support.xilinx.com. If
>> you need further assistance, please open a Webcase by clicking on
>> the
>> "WebCase" link at http://support.xilinx.com
>>
>> I am using Xilinx xc2v40 device and ISE 6.1. THe UCF file is:
>>
>> INST "u1" AREA_GROUP=g1;
>> AREA_GROUP "g1" RANGE=SLICE_X0Y0:SLICE_X9Y5,SLICE_X10Y0:SLICE_X15Y 3;
>> AREA_GROUP g1 MODE=RECONFIG;
>> AREA_GROUP g1 PLACE=CLOSED;
>>
>>
>> Could not find any help in the answers database at Xilinx.
>> Can someone please help me?
>>
>> Thanks in anticipation.
>> Aman

Have you asked Xilinx? Open a webcase and they'll give you the answer. I'd
guess that they probably are limited to rectangles, it would be pretty
hard to handle other shapes.

Hi,

Modular Design does not support the use of non-rectangular area group
ranges, http://support.xilinx.com/xlnx/xil_a...PagePath=16423


Miguel Silva