FPGA Central

hello,all
i have built an edk project(based microblaze) . Because my
application c code is very big,when generating linker script ,i put some
big sections into the ddr and others into bram in microblaze.finally,it
displays the results through rs232.
for now,i want to try to import the EDK Project with microblaze as
Sub-system into a ISE project and i use the cammand h "export to project
navigator",then it generate a system.ise file.but,when i put the
.system_stub.bit,system_stub_bd.bmm and my_project.elf(software bits
files
into the board ,it does not work well.
however,if i replace the my_project.elf to TestApp_Memory.elf
(linking script in bram not ddr),it works well.
who can tell me the reasnon ? what can i should do?thank you very
much..


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On Nov 3, 4:27*am, "gentel" <gente...@163.com> wrote:
> hello,all
> * * * i have built an edk project(based microblaze) . Because my
> application c code is very big,when generating linker script ,i put some
> big sections into the ddr and others into bram in microblaze.finally,it
> displays the results through rs232.
> * * * for now,i want to try to import the EDK Project with microblaze as
> Sub-system into a ISE project and i use the cammand h "export to project
> navigator",then it generate a system.ise file.but,when i put the
> .system_stub.bit,system_stub_bd.bmm and my_project.elf(software bits)
> files
> into the board ,it does not work well.
> * * * *however,if i replace the my_project.elf to TestApp_Memory.elf
> (linking script in bram not ddr),it works well.
> * * * *who can tell me the reasnon ? what can i should do?thank you very
> much..
>
> --------------------------------------- * * * *
> This message was sent using the comp.arch.fpga web interface onhttp://www..FPGARelated.com

and what magic loads the object into the extenal DDR memory?

maybe you forget the ram loader?

Antti

>On Nov 3, 4:27=A0am, "gentel" <gente...@163.com> wrote:
>> hello,all
>> =A0 =A0 =A0 i have built an edk project(based microblaze) . Because my
>> application c code is very big,when generating linker script ,i pu
some
>> big sections into the ddr and others into bram in microblaze.finally,it
>> displays the results through rs232.
>> =A0 =A0 =A0 for now,i want to try to import the EDK Project wit
microbla=
>ze as
>> Sub-system into a ISE project and i use the cammand h "export t
project
>> navigator",then it generate a system.ise file.but,when i put the
>> .system_stub.bit,system_stub_bd.bmm and my_project.elf(software bits)
>> files
>> into the board ,it does not work well.
>> =A0 =A0 =A0 =A0however,if i replace the my_project.elf t
TestApp_Memory.=
>elf
>> (linking script in bram not ddr),it works well.
>> =A0 =A0 =A0 =A0who can tell me the reasnon ? what can i should do?than
y=
>ou very
>> much..
>>
>> --------------------------------------- =A0 =A0 =A0 =A0
>> This message was sent using the comp.arch.fpga web interfac
onhttp://www=
>.FPGARelated.com
>
>and what magic loads the object into the extenal DDR memory?
>
>maybe you forget the ram loader?
>
>Antti
>
>thanks for your reply!when generating linker script,i put sections such a
.heap,.stack,.text,and.bss into the ddr ,it works well when downloading th
board in sdk.ram loader ?what do you mean?

---------------------------------------
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>On Nov 3, 4:27=A0am, "gentel" <gente...@163.com> wrote:
>> hello,all
>> =A0 =A0 =A0 i have built an edk project(based microblaze) . Because my
>> application c code is very big,when generating linker script ,i pu
some
>> big sections into the ddr and others into bram in microblaze.finally,it
>> displays the results through rs232.
>> =A0 =A0 =A0 for now,i want to try to import the EDK Project wit
microbla=
>ze as
>> Sub-system into a ISE project and i use the cammand h "export t
project
>> navigator",then it generate a system.ise file.but,when i put the
>> .system_stub.bit,system_stub_bd.bmm and my_project.elf(software bits)
>> files
>> into the board ,it does not work well.
>> =A0 =A0 =A0 =A0however,if i replace the my_project.elf t
TestApp_Memory.=
>elf
>> (linking script in bram not ddr),it works well.
>> =A0 =A0 =A0 =A0who can tell me the reasnon ? what can i should do?than
y=
>ou very
>> much..
>>
>> --------------------------------------- =A0 =A0 =A0 =A0
>> This message was sent using the comp.arch.fpga web interfac
onhttp://www=
>.FPGARelated.com
>
>and what magic loads the object into the extenal DDR memory?
>
>maybe you forget the ram loader?
>
>Antti
>
>thanks for your reply!when generating linker script,i put sections such a
.heap,.stack,.text,and.bss into the ddr ,it works well when downloading th
board in sdk.ram loader ?what do you mean?

---------------------------------------
This message was sent using the comp.arch.fpga web interface o
http://www.FPGARelated.com

On Nov 3, 9:57*am, "gentel" <gente...@163.com> wrote:
> >On Nov 3, 4:27=A0am, "gentel" <gente...@163.com> wrote:
> >> hello,all
> >> =A0 =A0 =A0 i have built an edk project(based microblaze) . Because my
> >> application c code is very big,when generating linker script ,i put
> some
> >> big sections into the ddr and others into bram in microblaze.finally,it
> >> displays the results through rs232.
> >> =A0 =A0 =A0 for now,i want to try to import the EDK Project with
> microbla=
> >ze as
> >> Sub-system into a ISE project and i use the cammand h "export to
> project
> >> navigator",then it generate a system.ise file.but,when i put the
> >> .system_stub.bit,system_stub_bd.bmm and my_project.elf(software bits)
> >> files
> >> into the board ,it does not work well.
> >> =A0 =A0 =A0 =A0however,if i replace the my_project.elf to
> TestApp_Memory.=
> >elf
> >> (linking script in bram not ddr),it works well.
> >> =A0 =A0 =A0 =A0who can tell me the reasnon ? what can i shoulddo?thank
> y=
> >ou very
> >> much..
>
> >> --------------------------------------- =A0 =A0 =A0 =A0
> >> This message was sent using the comp.arch.fpga web interface
> onhttp://www=
> >.FPGARelated.com
>
> >and what magic loads the object into the extenal DDR memory?
>
> >maybe you forget the ram loader?
>
> >Antti
>
> >thanks for your reply!when generating linker script,i put sections such as
>
> .heap,.stack,.text,and.bss into the ddr ,it works well when downloading the
> board in sdk.ram loader ?what do you mean? * * * *
>
> --------------------------------------- * * * *
> This message was sent using the comp.arch.fpga web interface onhttp://www..FPGARelated.com

i mean you need to write YOUR OWN code and ELF to something conversion
tools, and use some
flash or removable media to "bootstrap" your application

or use XMD during debugging

Antti

>On Nov 3, 9:57=A0am, "gentel" <gente...@163.com> wrote:
>> >On Nov 3, 4:27=3DA0am, "gentel" <gente...@163.com> wrote:
>> >> hello,all
>> >> =3DA0 =3DA0 =3DA0 i have built an edk project(based microblaze)
Beca=
>use my
>> >> application c code is very big,when generating linker script ,i put
>> some
>> >> big sections into the ddr and others into bram i
microblaze.finally,i=
>t
>> >> displays the results through rs232.
>> >> =3DA0 =3DA0 =3DA0 for now,i want to try to import the EDK Projec
with
>> microbla=3D
>> >ze as
>> >> Sub-system into a ISE project and i use the cammand h "export to
>> project
>> >> navigator",then it generate a system.ise file.but,when i put the
>> >> .system_stub.bit,system_stub_bd.bmm and my_project.elf(softwar
bits)
>> >> files
>> >> into the board ,it does not work well.
>> >> =3DA0 =3DA0 =3DA0 =3DA0however,if i replace the my_project.elf to
>> TestApp_Memory.=3D
>> >elf
>> >> (linking script in bram not ddr),it works well.
>> >> =3DA0 =3DA0 =3DA0 =3DA0who can tell me the reasnon ? what can
should=
> do?thank
>> y=3D
>> >ou very
>> >> much..
>>
>> >> --------------------------------------- =3DA0 =3DA0 =3DA0 =3DA0
>> >> This message was sent using the comp.arch.fpga web interface
>> onhttp://www=3D
>> >.FPGARelated.com
>>
>> >and what magic loads the object into the extenal DDR memory?
>>
>> >maybe you forget the ram loader?
>>
>> >Antti
>>
>> >thanks for your reply!when generating linker script,i put sections suc
=
>as
>>
>> .heap,.stack,.text,and.bss into the ddr ,it works well when downloadin
t=
>he
>> board in sdk.ram loader ?what do you mean? =A0 =A0 =A0 =A0
>>
>> --------------------------------------- =A0 =A0 =A0 =A0
>> This message was sent using the comp.arch.fpga web interfac
onhttp://www=
>.FPGARelated.com
>
>i mean you need to write YOUR OWN code and ELF to something conversion
>tools, and use some
>flash or removable media to "bootstrap" your application
>
>or use XMD during debugging
>
>Antti
>
>oh,i use the xilinx virtex_2 pro borad and it only has a cf card interfac
.and i can not understand fully what you have said .now i do not know ho
to do，can you tell me some detailed steps or pdf instructions?thanks ver
much..

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> >oh,i use the xilinx virtex_2 pro borad and it only has a cf card interface
>
> .and i can not understand fully what you have said .now i do not know how
> to do，can you tell me some detailed steps or pdf instructions?thanks very
> much.. Â* Â*

if you have systemace based board then you can load the image from CF
also
it does use the JTAG debug interface for software loading, this
however only
works if you load from ace file, if you load the bit file over jtag
with debug cable
the soft would not get initialized

otherwise creating an custom ram loader is one ore more MAN-WEEK of
work
this is the time YOU have to spend doing real work, asking for help
doesnt
count as work done

Antti

>> >oh,i use the xilinx virtex_2 pro borad and it only has a cf car
interfa=
>ce
>>
>> .and i can not understand fully what you have said .now i do not kno
how
>> to do=EF=BC=8Ccan you tell me some detailed steps or pd
instructions?tha=
>nks very
>> much.. =C2=A0 =C2=A0
>
>if you have systemace based board then you can load the image from CF
>also
>it does use the JTAG debug interface for software loading, this
>however only
>works if you load from ace file, if you load the bit file over jtag
>with debug cable
>the soft would not get initialized
>
>otherwise creating an custom ram loader is one ore more MAN-WEEK of
>work
>this is the time YOU have to spend doing real work, asking for help
>doesnt
>count as work done
>
>Antti
>thank you very much.thanks for your reply.

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