This was just posted in c.a.e, but could have potential for fast
simulation times in
FPGA developments ?
I presume the delay-simulations are OK with single precision 32 bit
floats ?
PDF article:
http://www.cs.berkeley.edu/%7Esamw/p.../cell/CF06.pdf
web article:
http://www.hpcwire.com/hpc/671376.html
With these speeds, it also looks like a nice device to put alongside a
FPGA....
-jg