FPGA Central

Hello,

I'm attempting to implement a hardware filter on an incoming video
signal (either S-video or composite) using a Xilinx V2Pro and a VDEC1
daughterboard from Digilent.

I'm attempting to test my HDL implementation, but can't seem to find a
way of simulating the video stream itself. Based on what I've read the
video will be in the formats found in ITU656 and ITU601 (NTSC). What
I'd like to do is have a file containing a digital stream in this
format, and use it in a testbench to verify my design.

The problem here is that I cannot seem to find either some method to
convert video or image files into such a stream, or an existing stream
for testing purposes. While I could (and am) write such a conversion
script myself, there is the risk that I'm misundestanding the format,
and will be testing my HDL module against an invalid data stream.

Try:
http://www.kd7lmo.net/ground_gnuradio_ota.html

about half way down there is an ntsc test pattern signal. The format (I
believe) is 8 msps complex in 16-bit I an Q samples.

If that's no good you can ask around the gnu radio message board to see if
someone will record some OTA samples for you.
-Clark

"Matt Fornero" <[email protected]> wrote in message
news:[email protected] ps.com...
> Hello,
>
> I'm attempting to implement a hardware filter on an incoming video
> signal (either S-video or composite) using a Xilinx V2Pro and a VDEC1
> daughterboard from Digilent.
>
> I'm attempting to test my HDL implementation, but can't seem to find a
> way of simulating the video stream itself. Based on what I've read the
> video will be in the formats found in ITU656 and ITU601 (NTSC). What
> I'd like to do is have a file containing a digital stream in this
> format, and use it in a testbench to verify my design.
>
> The problem here is that I cannot seem to find either some method to
> convert video or image files into such a stream, or an existing stream
> for testing purposes. While I could (and am) write such a conversion
> script myself, there is the risk that I'm misundestanding the format,
> and will be testing my HDL module against an invalid data stream.
>