FPGA Central

/proj/holistic/work/uhan/virtex5/tools/stampit


BRAM ( updated )
------
/proj/holistic/work/uhan/virtex5/tools/stampit/stampit.pl -design
/proj/holistic/work/uhan/virtex5/tools/stampit/templates/ramb36_rnr_ra36_rb36_wa36_wb36_maWRITE_FIRST_mbWRI TE_FIRST
-device rnr_120x30i -tile RAMB36 -rpm
/build/xfndry/HEAD/env/Databases/DeviceResourceModel/data/rainiers/rainier/model/lin64opt/x5vlx50t.rpm
-instance top -outdir
/proj/holistic/work/uhan/virtex5/tools/stampit/output/ramb36

> -device rnr_120x30i -tile RAMB36 -rpm

coooool

Ui (daniel) Han wrote:
> /proj/holistic/work/uhan/virtex5/tools/stampit
>
>
> BRAM ( updated )
> ------
> /proj/holistic/work/uhan/virtex5/tools/stampit/stampit.pl -design
> /proj/holistic/work/uhan/virtex5/tools/stampit/templates/ramb36_rnr_ra36_rb36_wa36_wb36_maWRITE_FIRST_mbWRI TE_FIRST
> -device rnr_120x30i -tile RAMB36 -rpm
> /build/xfndry/HEAD/env/Databases/DeviceResourceModel/data/rainiers/rainier/model/lin64opt/x5vlx50t.rpm
> -instance top -outdir
> /proj/holistic/work/uhan/virtex5/tools/stampit/output/ramb36
>

Does that mean that ramblocks on the Virtex-5 are 36kbits now ?


Sylvain

Accidents happen.
This was obviously not a newsgroup message.
All of us have clicked a wrong button at a wrong time, at least once.
We are sorry for the confusion this created.
Peter

nice accident !

at least we know that number 5 isnt skipped in the Virtex roadmap

Antti

"Antti" <[email protected]> writes:
> nice accident !
> at least we know that number 5 isnt skipped in the Virtex roadmap

Assuming that the Marketing department doesn't rename it before offical
introduction. Things like that sometimes happen.

Presumably the Virtex 5 (or whatever it's going to be called) is the
65 nm part mentioned in a recent Xilinx press release.

What I'd like to see on the roadmap would be some very-low-leakage
Spartan parts, for use in battery powered devices. They wouldn't need
to be anywhere near as fast as the Spartan 2, nor as dense. Maybe it
could be done with thick oxide in 180, 250, or perhaps even 350 nm.
Gotta do soemthing with all that excess fab capacity in older processes;
might as well make low-leakage FPGAs. :-)

Alternatively, big low-power CPLDs with some RAM blocks would be nice.
Once upon a time Intel made some medium-ish sized ones (by the standards
of that time) in which each group of macrocells could be reconfigured
as a small RAM. Then they transferred the product to Altera and it
was quickly discontinued. Sigh.

Eric Smith wrote:

> "Antti" <[email protected]> writes:
>
>>nice accident !
>>at least we know that number 5 isnt skipped in the Virtex roadmap
>
>
> Assuming that the Marketing department doesn't rename it before offical
> introduction. Things like that sometimes happen.
>
> Presumably the Virtex 5 (or whatever it's going to be called) is the
> 65 nm part mentioned in a recent Xilinx press release.

Would make sense.

> What I'd like to see on the roadmap would be some very-low-leakage
> Spartan parts, for use in battery powered devices. They wouldn't need
> to be anywhere near as fast as the Spartan 2, nor as dense. Maybe it
> could be done with thick oxide in 180, 250, or perhaps even 350 nm.
> Gotta do soemthing with all that excess fab capacity in older processes;
> might as well make low-leakage FPGAs. :-)

I have a sample on the bench that draws 2.4uA, but it is not a Spartan
FPGA...

-jg

Jim Granville wrote:

> Eric Smith wrote:
>
>> "Antti" <[email protected]> writes:
>>
>>> nice accident !
>>> at least we know that number 5 isnt skipped in the Virtex roadmap
>>
>>
>>
>> Assuming that the Marketing department doesn't rename it before offical
>> introduction. Things like that sometimes happen.
>>
>> Presumably the Virtex 5 (or whatever it's going to be called) is the
>> 65 nm part mentioned in a recent Xilinx press release.
>
>
> Would make sense.
>
>> What I'd like to see on the roadmap would be some very-low-leakage
>> Spartan parts, for use in battery powered devices. They wouldn't need
>> to be anywhere near as fast as the Spartan 2, nor as dense. Maybe it
>> could be done with thick oxide in 180, 250, or perhaps even 350 nm.
>> Gotta do soemthing with all that excess fab capacity in older processes;
>> might as well make low-leakage FPGAs. :-)
>
>
> I have a sample on the bench that draws 2.4uA, but it is not a Spartan
> FPGA...

I doubt anyone would be confused, but just in case, no, this is _not_
a Virtex-5 sample...

-jg